Version : 3.5 Total pages : 15 Date : 2004. 9. 24 (Not include cover page)
APPLICATION NOTE MODEL NAME:
UPS051
T he c on te nt o f t his t ec h nic al i n fo r ma t io n is s u bj ec t to change without notice.
Record of Revision Version
Change Date
3.5
24/Sep/2004
Content Modify document form
1
Contents: A. Object .......................................................................................................................................3 B. Applicable TFT-LCD models ................................................................................................3 C. Block diagram .........................................................................................................................3 D. Conversion process from an image data array to UPS051’s format..........................3 1. Input format for UPS051 .......................................................................................................3 2. Implementation example of conversion ................................................................................3 2-1. Calculation of the wedding cycle ................................................................................3 2-2. Extration of display data .............................................................................................3 E. Typical reference circuit ........................................................................................................3 F. Detail timing .............................................................................................................................4 Appendix .......................................................................................................................................5
2
A. Object This application note contains additional information for using AUO COG series TFT-LCD module with UPS051 controller. There are two major topics contained in this note, they are “Typical reference circuit” and “Conversion process from an image data array to UPS051’s format”.
B. Applicable TFT-LCD models AUO’s COG series panels, including A015AN03, A018AN02, A025CNXX, A035CNXX, A040CNXX, A056DNXX, A068ENXX, A070FWXX.
C. Block diagram Please refer to Fig.1 for the application concept of UPS051.
D. Conversion process from an image data array to UPS051’s format 1. Input format for UPS051 UPS051 implements an 8-bit data to drive each TFT-LCD’s primary color. To reduce the I/O number, UPS051 accepts the color data in a sequence format, those are R0〜R7, G0〜G7 & B0〜 B7 which come from display memory and are extracted into the D0〜D7 corresponding to the color filter arrangement of LCD. Please refer to Fig.2-b for the required format which UPS051 is operated under the normal scan mode (LR:H, UD:L) as an example. To allow customer to drive the traditional CRT-TV & UPS051 simultaneously, UPS051 can accept the non-symmetric clock. That means customer can use the same clock (V-CLK) to drive DAC for CRT-TV and to generate the “wedding” clock (D-CLK) which will synchronize the UPS051’s operation. Please also refer to Fig.2-b for the “wedding” clock, D-CLK. 2. Implementation example of conversion To give customer more clear idea about the conversion, we present an example here, and its source data array is VGA (640×3×480) and the target format is UPS051’s 280×220 mode. The procedure of implementing a conversion circuit is as below. 2-1. Calculation of the wedding cycle There are 640 pixel’s data for each horizontal line stored in the display memory, and each pixel contains 3 primary color dots’ data. On the other hand, when UPS051 is operated at 280×220 mode, only 280 dots at each LCD horizontal line can be displayed. So the abundant pixel data in VGA display memory should be extracted to a limited number, which is 280 dot for each horizontal line. To get the wedding cycle, we calculate 640÷(280/3)＝6.86≒7 This means only 3 dots (one pixel) can be extracted from every 7 pixels at VGA memory. Since UPS051 latchs each input data at the rising edge of every D-CLK, so the D-CLK’s frequance is 3/7 V-CLK. For example, at VGA mode, the V-CLK is 12.27MHz, and the D-CLK can be got by “MASKING 4 V-CLK IN EVERY 7 V-CLK”. Please refer to Fig.2 for the wedding’s operation. 2-2. Extration of display data From the above calculation, only 3 dots data can be extracted from every 7 pixels. To accommodate the special arrangement of LCD’s color filter, the R.G.B data are extracted from different pixels’ positions. Please refer to Fig.3 for these data extraction. Due to the “Delta” type arrangement of LCD’s color filter, this means the color sequence and position of each primary color will be different at odd lines and even lines. So the extraction should also follow this difference. Please follow the corresponding sequence under different conditions which are shown in Tab.1
E. Typical reference circuit Please refer to Fig.4 for the reference circuit, which contains all the pheripheral circuitry of UPS051
3
when it is used to drive the AUO’s COG series TFT-LCD.
F. Detail timing Please refer to the data sheet of UPS051.
4
AUO’S COG TFTLCD
Appendix
5
Fig (a).
Fig (b).
6
8
R2
B2
G3
R3
B4
G4
R5
B
R G
B
R G
R G
B
R B
R
R G
B
LCD’s color filter arrangement
G
B
G
Fig 3. Extraction example of display data from memory to UPS051
B1
G1
G
B
G
+15V
+15V
VCCD
-10V
C1
+
-10V
@106F
473F
R2
473F
R3
473F
R4
473F
R7
473F
R8
473F
D22
D23
+
C2
R1
VCCD
VCCD
@106F
VCC1
VCC1
R5
R6
VCCD
333F
GNDS
C6
R12
D24
D12
R11 34
33
VIN
VCC4
36
37
38
39
40
41
42
35 NPC
GND4
IOUT
VTEST
GR_IN
VOUT3
RSB
43 RSA
VOUT2
45
46
44 VOUT1
VCC5
GND5
VCC3 GND3
[DDX7]
Q1H_OUT
15
GND2
32
D26
31
30 C7 @104I
29
28
27
RSC
26
FBK2
25
D13
FBK1
24
PWM1
23
C9 @104I
PWM2
VCC1
21
VCC1
PWM3
18
VCC2
17
FBK3
+15V
C12 @104I
C11 @104I
R15
+15V
D4
VCCD D25
PFRP
101F
R17
C13
Hsync
R16 000F
@104I D14
DCLK
D7 D9
VCCD
D5
6
5
7
8
D6
R18 223F
+I/P B GND
-I/P B+I/P A
O/P A
O/P B -I/P A
V+
D16
+ @106F
R27
VR503C
R21
R19
D19
101F
D18
101F
GND VCC VGL VGH STVR STVL CKV U/D OEV
D10 : D11 :
VCOM VCOM
D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
L/R Q1H OEH STHL STHR CPH3 CPH2 CPH1 DVDD DVSS VA VB VC AVDD AVSS
: : : : : : : : : : : : : : :
D17
BRT1 VR503C
D10
101F
-10V R24 103F
R25 103F
203F
: : : : : : : : :
4
3
2
1 R22 103F
PFRP
R20
VCDC1
+
-10V
C16
D15
NJM3414AM
C14 @106F
D1 D2 D3 D4 D5 D6 D7 D8 D9
Vsync
101F
VCCD
U2
ELCO26PA
JP1 PIN ASSIGNMENTS
@104I
ENAB
R14 472F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
D20
C10
20 FBK3 19
JP1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
D2
22
16
14
13
12
[DEM]
PFRP_OUT
VCC2
[VSD]
PWM_OUT3
CPH1_OUT
[HSD]
CPH2_OUT
GME
FBK3
GND1
CPH3_OUT
1
64
PWM_OUT2
[DDX6]
11
63
[DDX5]
VCI
1
PWM_OUT1
10
3
8
VCC33
62
SW1
UPS051
[DDX4]
VCC1
Note
VCCD
FBK1
9
61
VCC1
HOE_OUT
60
FBK2
8
58 59
ELCO18PA
VCC3IO
V_CK
57
RSC
GND1
VOE_OUT
56
UD_OUT
6
@104I
55
LR_OUT
[DDX3]
7
54
C8
[DDX2]
STVL
DDX0 DDX1 DDX2 DDX3 DDX4 DDX5 DDX6 DDX7
[V_DIR]
5
53
[DDX1]
STVR
52
VCCD
CLK
D21
IN1 [H_DIR]
STHL
Hsync
Vsync
D1
[DDX0]
3
51
IREF
4
50
STHR
911
[DCLK]
49
R13
2
JP2
VG
VREF
48
U1
47
750F
GNDB
GNDD
@106F
RSB
@104I
000F
ENAB
C3
D8 RSA
R10 000F
VCC2 GNDB VCC1 GNDS Hsync Vsync CLK ENAB GNDD
VCCD
C5 @104I
C4 @104I
R9 333F
GNDD
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
223F
+
VCC2
VCC2
D3
@106F -10V
VCOM
D11
+ C15
R23 102F
-10V
D1
MA158
R26 101F
Fig. 4-1 Typical reference circuit of UPS051 (gernal 26pin product)
Title Size A2 Date:
UPS051 driving board Document Number Thursday, July 03, 2003
Rev 2 Sheet
1
of
4
9
+15V
+15V
VCCD
-10V
C17
R28
473F
R29
473F
R30
473F
R31
473F
R34
473F
R35
473F
D10
+
-10V
@106F
D9
+
C18
VCCD
VCCD
@106F
VCC1
VCC1
R32
R33
VCCD
333F
R37 000F
C22
R39
D12
R38 34
33
VIN
VCC4
36
37
38
35 NPC
GND4
IOUT
39 GR_IN
41 RSB
VOUT3 40
43 RSA
VOUT2 42
45
46
48
VOUT1 44
VCC5
GND5
VTEST
PWM_OUT1
[DDX5]
PWM_OUT2
[DDX6]
VCC3
[DDX7]
GND3
Q1H_OUT
15
R43
R41 472F
R44
C29
GND2
C23 @104I
29
28
27
RSC
26
FBK2
25
D3
FBK1
24
PWM1
23
C25 @104I
PWM2
21
VCC1
C26 @104I
PWM3
18
FBK3
VCC2
17
+15V
C28 @104I
C27 @104I
+15V
D16
VCCD D14
PFRP
101F
Vsync
101F
Pin Assignment
Hsync
R42 000F
@104I
VCCD
D2
DCLK
D20 D19
VCCD
6
5
7
8
D22
+I/P B GND
-I/P B +I/P A
O/P A
O/P B -I/P A
V+
D13 R46 C30 @106F
VCDC2
+ @106F
R54
R48
D4
101F
D5
101F
D6
101F
-10V R51 103F
R52 103F
203F
R47
VR503C
4
3
2
1
+
R49 103F
PFRP
D1
NJM3414AM
-10V
C32
D18
R45 223F
U4
BRT2 VR503C
D15
+ C31
R50 102F
@106F -10V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
D17 VCC1
20 19
JP3
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
CON24
22
16
14
13
12
VCI
11
ENAB
10
[DEM]
PFRP_OUT
VCC2
[VSD]
PWM_OUT3
CPH1_OUT [HSD]
CPH2_OUT
GME
FBK3
GND1
CPH3_OUT
VCC1
64
UPS051
[DDX4]
1
VCC33
63
1
8
FBK1
HOE_OUT
62
SW2 3
VCC1
9
Note VCCD
RSC FBK2
8
60 61
30
VCC3IO
VOE_OUT
58 59
ELCO18PA
GND1
V_CK
57
UD_OUT
6
56
[DDX3]
7
@104I
55
LR_OUT
STVL
C24
[DDX2]
5
54
DDX0 DDX1 DDX2 DDX3 DDX4 DDX5 DDX6 DDX7
[V_DIR]
STHL
53
32
31
[H_DIR]
[DDX1]
STVR
52
VCCD
CLK
D7
IN1
[DDX0]
3
50 51
Hsync
4
911
STHR
R40
IREF
[DCLK]
49
2
JP4
VG
VREF
47
U3
GNDD
D8
750F
GNDB
ENAB
@106F
D21
@104I
000F
Vsync
C19
RSB
RSA
GNDS
VCC2 GNDB VCC1 GNDS Hsync Vsync CLK ENAB GNDD
VCCD
C21 @104I
C20 @104I
R36 333F
GNDD
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
223F
+
VCC2
VCC2
-10V
D2
MA158
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
: : : : : : : : : : : : : : : : : : : : : : : :
STHL OEH Q1H CPH1 CPH2 CPH3 GND VB VR VG N.C. L/R STHR AVDD VCOM VGH VCC STVL OEV CKV U/D STVR N.C. VGL
D24
R53 101F
VCOM
Fig. 4-2 Typical reference circuit of UPS051 (For A025CN00/01, A035CN00/01)
Title Size A2 Date:
UPS051 driving board Document Number Thursday, July 03, 2003
Rev 2 Sheet
2
of
4
10
+15V
+15V
VCCD
-10V
C33
R55
473F
R56
473F
R57
473F
R58
473F
R61
473F
R62
473F
D26
+
-10V
@106F
D27
+
C34
VCCD
VCCD
@106F
VCC1
VCC1
R59
R60
VCCD 333F
C36 @104I
R63 333F
GNDD
C38
R66 000F
@106F
D28
RSB
R65
34
35
36
37
38
39
40
41
42
43
44
45
46
47
33 VCC4
VIN
NPC
GND4
IOUT
VTEST
GR_IN
VOUT3
RSB
VOUT2
RSA
VOUT1
VCC5
GND5
VG
VREF
GND3
CPH3_OUT
FBK3
CPH2_OUT
PWM_OUT3
CPH1_OUT PFRP_OUT 16
Q1H_OUT 15
[VSD] 14
[HSD]
VCC2
13
[DEM]
1
64
[DDX7]
GME
1
VCC3
12
63
3 8
VCC33
PWM_OUT2
[DDX6]
GND1
Note VCCD
[DDX5]
11
62
PWM_OUT1
VCI
61
SW3
[DDX4]
10
60
FBK1
UPS051
VCC1
59
VCC1
9
58
FBK2
HOE_OUT
GNDD
ELCO18PA
RSC
VCC3IO
8
57
GND1
V_CK
56
UD_OUT
7
@104
55
[DDX3]
VOE_OUT
54 C40
LR_OUT
6
DDX0 DDX1 DDX2 DDX3 DDX4 DDX5 DDX6 DDX7
53
[V_DIR]
[DDX2]
STVL
CLK
[H_DIR]
5
VCCD
D25
[DDX1]
STVR
Vsync
D1
IN1
[DDX0]
4
52
STHL
51 Hsync
IREF
3
50
STHR
911
[DCLK]
49 R67
2
JP6
48
750F U5
JP5
D16
@104I
GNDB
ENAB
C35
D8 RSA
GNDS
VCC2 GNDB VCC1 GNDS Hsync Vsync CLK ENAB GNDD
VCCD
C37 @104I
R64 000F
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
223F
+
VCC2
VCC2
GND2
32 D30
31 30 29
C39 @104I
28 27
RSC
26
FBK2
25
D17
FBK1
24
PWM1
23
C41 @104I
PWM2
22
D2 VCC1
21
D24
Con30
@104I PWM3
FBK3
18
VCC2
17
C43 @104I
+15V
C44 @104I
+15V
D4
VCCD D29
PFRP
PFRP
ENAB R69
R68 472F
101F Vsync
R71 101F
Hsync
C45
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
C42
20 19
VCC1
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30
R70 000F
JP301 PIN ASSIGNMENTS D1 D2 D3 D4 D5 D6 D7 D8 D9
: : : : : : : : :
GND VCC VGL VGH STVR STVL CKV U/D OEV
D10 : D11 :
VCOM VCOM
@104I VCCD
D18
DCLK
D7 D9
VCCD
D5
5
6
7
8
D6 R72 223F
U6
+I/P B
R73
GND
-I/P B +I/P A
O/P A
O/P B -I/P A
V+
D20
C46 @106F
@106F
R81
BRT3 VR503C
D23
101F
D22
101F
D21
101F
D10
-10V
R78 103F
R79 103F
203F
R75
VR503C
4
3
2
1
+ PFRP
R74
VCDC3
+
-10V R76 103F C48
D19
NJM3414AM
D11
+ C47
R77 102F
D3
@106F -10V
-10V
D3
MA158
R80 101F
VCOM
D12: D13: D14: D15: D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30
GLED1 VLED1 VLED2 GLED2 : : : : : : : : : : : : : : :
L/R Q1H OEH STHL STHR CPH3 CPH2 CPH1 DVDD DVSS VA VB VC AVDD AVSS
Fig. 4-3 Typical reference circuit of UPS051 (For A025CN03, A035CN02) Title UPS051 driving board Size A2 Date:
Document Number Friday, July 04, 2003
Rev 2 Sheet
3
of
4
11
For 1.5" ~ 4" inverter T1 1
Note
VCC1 C49 @476C
+
1
+6V
L1 %150uHD D4 MA152K
C50 @103 PWM1
PWM1 R82
F1
L3
%22uHD
VCC1
Q1 2SD1119
101F
VCC1 FBK1 L4
R83 124F
+15V
3
C51 @476C
+
C52
2
R84 103F
@476C
%22uHD VCCD
C56 @104I
2
9
3
8
4
7
5
6
R85 103F
C53
5
Q3 2SD1005BV
Q2 2SD1005BV
VCC2
@476C
JP7
8
1 2
7
VCCD
6
C55
NOTE
C57 @106F
GND
SHIELD1
C59
9
H.V. 4
VCC1
VCC5
10
@473C R87 303F
101F
FBK1
10
+
R86
C54 @476C
F1AB
+15V
1
1
VCC5
L2 %150uHD
+
C58
VCC2 C61 C60 @104I
@476C
SHIVP181A
@103 PWM2 PWM2
R88
Q4 2SB1188
1201F
-10V D5 MA701A
R89 124F
-10V
C62 @476C
+
L5 %150uHD
For 5.6", 6.8" & 7.0" inverter FBK2
FBK2
T1
R90 303F
1
1
10
2
9
3
8
4
7
5
6
10
NPO 25 pF/ 3 KV
+12V 2 L6
VCC1
C63
%220uHE
3
9
H.V.
8
100uF/16V
@476C
GNDS
C67
GNDB @103 GNDD
R94
PWM3
PWM3
222F
FBK3
C65 82N/63V
R91 752F
VCC2 C66
4
5
R92 752F
+
JP8 1 2
+ C64
7
6
STC-1107-110 (EFD-15) L7 %150uHD
Q5
D6 MA701A Q7 2SD1119
+6V R93 303F
Q6 2SC4672(DK)
2SC4672(DK)
+ C68 @476C
FBK3 R95 303F
Title Size A3 Date:
UPS051 driving board Document Number Thursday, July 03, 2003
Rev 2 Sheet
4
of
4
Fig 4-4 Typical reference circuit of UPS051 (Power) 12
Note: 1. Resolution setting LCD size
Resolution
RSA
RSB
RSC
T11
1.5" & 1.8"
280
Low
Low
Low
BLC13/1025
2.5" & 3.5"
480
High
High
High
BLC13/1193
4"
480
High
High
High
BLC13/1193
5.6"
960
High
Low
High
6.8"
1152
Low
High
Low
7.0"
1440
Low
High
High 3.Bits data input setting: (D5 ~ D0)
2. PWM function un-used Pin
Assignment
Set
Pin
Assignment
Set
Pin
Assignment
Setting
24
PWM_OUT1
Open
25
FBK1
High
50
DDX0
Lo
23
PWM_OUT2
Open
26
FBK2
Low
51
DDX1
Lo
19
PWM_OUT3
Open
20
FBK3
High
52
DDX2
D0
53
DDX3
D1
57
DDX4
D2
58
DDX5
D3
59
DDX6
D4
60
DDX7
D5
4. VCC3IO setting VCC3IO Input
Input signals* level
VCCD(5V)
5V
VCC33(3.3V) 3.3V * Input signals contain: DCLK, HSD, VSD, V_DIR, H_DIR, DDX0 ~ DDX7. 5. ENAB pin setting: Please always pull low for Pin64 [DEM] in UPS051. 6. STVR (UPS051) should connect to STVL (panel). STVL (UPS051) should connect to STVR (panel). STHL (UPS051) should connect to STHL (panel). STHR (UPS051) should connect to STHR (panel).
13
Table.1 Color sequence for different modes. UD (Note 1)
Low
Low
High
High
LR (Note 2)
High
Low
High
Low
Odd Line
GBR
GRB
BRG
BGR
Even Line
BRG
BGR
GBR
GRB
Odd Line
GBR
RBG
RGB
BGR
Even Line
RGB
BGR
GBR
RBG
Display REesolution
280×220 (1.5” / 1.8”)
480x234 (2.45” / 3.5”)
Note 1: UD is an Up/Down scanning direction control pin of UPS051. Note 2: LR is a Left/Right scanning direction control pin of UPS051. When LR is high, the scanning direction is from “Left to Right”. When LR is low, the scanning direction is from “Right to Left”. Note 3: The sequence specified in each column represents the order of data which should be sent to UPS051 for cycle #1, 2, 3, 4, 5.
Left to Right
G
…………
G
R
B
B
R
B
R
R
R
Left to Right
R
R G
R
B
…………
R
B
G
G
G B
Down to Up
B R
G
………
………
Down to up
G B
G
R
B
B
G B
R
G
Up to down
Up to down
B
G
Right to Left
Right to Left Fig. 5 1.5”/ 1.8” Color filter arrangement
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Left to Right B R G
R G
B
G B
…………
R
B R
G
R
B R
G
Left to Right
R …………
B
G
G B
R
B R
G
B
Down to Up
G B
R
B
………
G
G B
………
Down to up
R
R
Up to down
Up to down
G
Right to Left
Right to Left
Fig.6 2.5”/ 3.5” Color filter arrangement
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