The information in this document is believed to be accurate and reliable. However, GESPAC assumes no responsibility for errors and inaccuracies in this document. GESPAC reserves the right to make changes and improvements to this specification at any time and without notice. G-64, G-96, G96+ and GESPAC are registered trademarks of GESPAC S.A.

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FOREWORD

The G-64 bus concept was defined by GESPAC in 1979 to meet the requirements of small, real-time industrial microcomputer systems, The G64 bus is an open architecture requiring no license for its use. Now a de facto industry standard, the G-64 bus concept, which includes the G-64, G-96 and G-64+ specifications , is supported by many independent board manufacturers around the world. The G-64 bus concept has been adopted by an ever increasing number of customers in all basic industries. The purpose of this manual is to sep up a reference specification to permit third party manufacturers as well as users, to develop compatible modules with the certitud that they will fully comply with the G-64 standard. All companies designing G-64 compatible modules can get information and support from GESPAC and can apply for inscription in the G-64 User's and Manufacturer's group. This manual is the fourth edition of the G-64 Specifications Manual. This specification unifies the G-64 and G-96 specifications described in the third edition. It provides complete details on the multi-processor arbitration, message passing protocol and specifies the upward compatible extension of the bus to 64-bit of data.

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CHAPTER 1 GENERAL INFORMATION

1.1 INTRODUCTION The specification has been written to ensure full compatibility between the G-64 Euroboard Manufacturers. The G-64 bus has been designed to handle effectively and economically 8-bit, 16-bit, 32-bit microprocessor based systems. G-64 is the generic trademark for the bus concept. Technically, the G-64 is a layered architecture comprising several levels of complexity and compliance, all of which are upward compatible. This layered architecture provides unprecedented flexibility and the ability to choose the cost effective implementation for a given application. The G-64 bus concept is processor independent as the most popular 8, 16, 32-bit processors are available from one of the several G-64 manufacturers. The most basic implementation is the G-64 specification which includes all necessary signals for the implementation of 8-bit systems, synchronous I/O interfaces, and simple 16-bit systems. The G-96 specification extends the memory addressing capability of the bus to fully support 16-bit microsystems, asynchronous I/O interfaces, and parallel decentralized multiprocessing capability. The G-96+ describes a fully upward compatible scheme for support of 32-bit data transfers on the bus.

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The G-64 bus supports a pre-decoded memory map for the implementation of I/O modules. This map is validated by the VPA (ValidPeripheralAddress) signal and address lines A0 through A9. This, in turn, allows to design G-64 bus compatible I/O modules that require very little component overhead. The interrupt structure includes 6 interrupt lines, 1 interrupt acknowledge and 1 daisy chain which allow implementation of non-vectored or prioritized vectored interrupt philosophy. A power-fail line is supported by the bus to inform the processor(s) and other modules on the bus of an imminent loss of power. In single-processor environment, the G-64 bus supports multiple DMA sources. The DMA operations are handled by BRQ (Bus Request) , BGRT (Bus Grant) and BBUSY (Bus Busy) signals and use the same daisy chain as the interrupts to set up priority between multiple DMA module requesters. For support of multi-processor, the G-64 implements a fully asynchronous, decentralized parallel arbitration scheme. This simple but powerful architecture uses 9 lines for controlling the access to the bus by up to 31 masters. Each board contains the arbitration circuitry, thus making a G-64 system much more fault tolerant than an equivalent system based on a centralized architecture. The multi-processing specification of the G-64 bus supports a very efficient message passing mechanism. These messages allow fast communication between masters as well as interrupts, called "events", between peripherals and masters on the bus.

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All G-64 compatible products can be identified by these logos:

1.2 TYPE OF MODULES SUPPORTED In a single processor G-64 bus system, two types of boards are supported: 1) Masters:

CPU boards - controls the bus - can receive interrupts

2) Slaves:

Memory boards - could generate interrupts I/O boards - can generate and eventually receive interrupts - cannot take control of the bus (except for DMA operations)

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1.3 FEATURES

8

1.4 SPECIFICATIONS A summary of the G-64 bus specifications is given in table 1.1. The signal name and pin assignment of the G-64 bus connector are identified in the table 1.2.

*Current necessary and specified only for use in un-terminated backplanes. Use of 48 mA drivers is recommended in all cases. Table 1.1 Specifications

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Note: Terms in [brackets] correspond to the old name of the signal as defined in release 2 of the G-64 specifications manual. Terms in italic correspond to the signals of the G-64+ bus Table 1.2 G-64 bus signals

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CHAPTER 2 MECHANICAL SPECIFICATIONS 2.1 INTRODUCTION This section of the specification manual defines the mechanical requirements of the connectors, boards, and backplanes used in a G-64 bus compatible environment. 2.2 G-64 CONNECTORS The backplane of the G-64 bus uses a standard DIN 41612-C female type connector. G-64 modules use the corresponding male connector. These are indirect pin-in-socket connectors which ensure very reliable contact and superior mechanical characteristics. Physical dimensions for implementation are shown in fig. 2.1b.

Fig.2.1a Module connector for G-64 standard.

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Fig.2.1b Backplane connector for G-64 standard.

2.3 G-64 MODULES G-64 modules use the standard single Eurocard format 100 mm x 160 mm x 1.6 mm. A free space between the side edges of the board and components must be respected for the use of card guides. The component height mounted on G-64 boards must not exceed 15 mm. The leads height must not exceed 3 mm. Spacing between slots is 20.32 mm (0.8" spacing). The G-64 Bus interface connector is mounted on the board back edge while the I/O connectors are placed on the front edge. Mechanical characteristics und usable space of the G-64 modules are illustrated in fig. 2.2.

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2.4 BACKPLANE The backplane is a printed circuit with connectors wired together by a set of bussed lines. The backplane also includes a connector for the power supply, holes for fixing card guides, and pre-positioned holes for mechanical mounting in different rack types. Optinally, backplanes can be supplied with jumper positions used to the short-circuit the daisy chain on unoccupied slots between two modules. Different backplane lengths are used for 4 to 20 connectors numbered1,2,3......20 from right to left when looking at the backplane from the board side. Dimensions and mechanical characteristics for the G-64 bus are illustrated in fig. 2.3.

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Fig. 2.2 G-64 Module mechanical characteristics

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Fig. 2.3 G-64 backplane mechanical characteristics

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CHAPTER 3 ELECTRICAL SPECIFICATIONS

3.1 INTRODUCTION This section defines the electrical characteristics of the signals and the board materials for the G-64 bus. The following items are discussed below : the power supply , the backplane, the bus termination, the connectors, the drivers, the receivers, and the transceivers.

3.2 POWER SUPPLY The G-64 bus must be supplied by 3 voltages: +5 Vdc, +12 Vdc and -12 Vdc. The +5 Vdc standby is used for battery backup applications like CMOS RAM, calendar, and time-of-day devices. The boards can be supplied with the standby power either from the bus (+5 V BATT) or from a local on-board battery. When a board does not use the standby power, it should be connected to the normal +5 supply.

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*The tolerance must be respected throughout the backplane length. Table 3.1 Power supply specification

3.3 BACKPLANES Two types of backplanes are considered here, one which is 2-layer nonterminated and another which is 5-layer terminated by resistor networks.

3.3.1 BACKPLANE WITHOUT TERMINATORS Applications which operate at a transfer rate up to 2 Mbytes per second can use a 2 side printed circuit backplane. The backplane is not terminated and can support also low power (CMOS) applications. The modules operating on this type of backplane can be equipped with 24 mA drivers devices which allow a configuration for a system using up to 20 modules.

3.3.2 BACKPLANE WITH TERMINATORS For systems operating at a transfer rate up to 40 Mbytes per second, a multilayer printed circuit is used for the backplane. The backplane is not terminated and can support also low power (CMOS) applications. The

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modules operating in this type of backplane can be equipped with 24 mA driver devices which allow configuration for a system using up to 20 modules.

3.3.3 BACKPLANE SPECIFICATIONS The specifications for the backplane with and without terminators are shown in table 3.2. There are several techniques to build multi-layer backplanes. However, the signal characteristic impedance should not be much lower than 100 ohms, thus it is necessary to use a structure as it is illustrated in fig. 3.1 (microstrip lines).

Fig. 3.1 Multi-layer backplane structure

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Table 3.2 Backplane electrical characteristics 3.4 BUS TERMINATORS A Thevenin network terminator is used on each end of the G-64 bus for all signals except the daisy chain. The terminator networks must have the lowest possible equivalent impedance to approach the one of the backplane. The purpose of terminators is essentially to reduce the reflection signal effect and provide pull-up for wired-ored lines driven up open collector devices. A 330/470 Ohm network can be used to terminate the bus signals at each end of the backplane. The buffer devices must be of the type 48 mA to drive up to 20 modules and the terminators on the bus.

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The Thevenin networks used on the G-64 bus are illustrated in fig. 3.2.

Fig. 3.2 G-64 bus termination 3.5. G-64 BUS CONNECTOR The G-64 bus uses DIN 41612-C connectors which are characterized by the IEC DIN 41610 specification. The parameters in the table 3.3 are extracted from the IEC 603-2 specification class 2.

Table 3.3 Electrical specifications for backplane and board connectors

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3.6 DRIVER CHARACTERISTICS The G-64 bus uses 3 types of drivers: low current totem pole, open collector, and tri-state. The low current totem pole driver is used only for the daisy chain line. The open-collector driver is used on the lines which have multiple signal sources. Only one driver can be active at time.

* The drivers are specified for a terminated backplane. For a non-terminated backplane, the open collector and three-state driver specifications are the same except IOL min=24 mA and IOH = -2 mA. ** Terminator network voltage or VCC with pull-up resistor. Recommended devices: -Totem pole: Any low-power Schottky device -Open collector: 74LS38, 75451, 75452, 74LS641-1, 74LS642-1, or equivalent driver/ transceiver device. -Tri-state: 74F24X, 74LS64X-1,8T95-8T98 or equivalent driver/ transceiver. Table 3.4 Driver device characteristics

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3.7 RECEIVER CHARACTERISTICS Receivers with hysteresis of 0.2 V min. are required for all input control lines (strobes, validation signals). It is also recommended to use receivers with hysteresis for all other signals (address and data). The receiver should have an input diode forcing a max. input clamp voltage of -1.5V. The receiver characteristics are shown in the table 3.5.

Recommended device: 74LS24X, 74F24X,74LS64X or equivalent receiver/transceiver Table 3.5 Receiver device characteristics

3.8 TRANSCEIVER CHARACTERISTICS The transceivers must have the same characteristics as those defined separately for the drivers and receivers, with a combined CIN/COUT of 18 pF max. Recommended devices: 74LS64X-1 or equivalent transceivers.

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3.9 SIGNAL ELECTRICAL CHARACTERISTICS The signal states are as follows: Low level, High level Transition low to high level (rising edge) Transition high to low level (rising edge) These levels are illustrated in the fig. 3.3 below.

Fig. 3.3. Signal levels

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CHAPTER 4 BUS SIGNAL DESCRIPTION 4.1 INTRODUCTION The following paragraphs define the different signals implemented in the general G-64 bus specification. This description includes a brief description of each signal, its electrical specification, and its use. More details on most of these signals, their dynamic characteristics and interactions are given in the following chapters. Many of these signals are applicable only if it is necessary to meet the higher levels of the G-64 bus specifications. These are clearly mentioned for each signal.

4.2.1

D0 - D15 (pin 19a - 26a and 19b - 26b)

- Applicable to G-64, G-96, G-96/32 and G-96/64. - Data bus: Tri-state negative logic signal, 48 mA. - Origin: Bus Master (CPU module), memory and peripheral modules. These 16 bi-directional lines are used for data transaction. A data transfer can be of 8 or 16-bits. 8-bit microprocessor systems must use data lines D0 - D7 . In a 16-bit system, it is possible to address separately the low order byte (D0 - D7) or the high order byte (D8 - D15). DS0 must be asserted for the low order byte transfer and DS1 for the high order byte. Asserting DS0 and DS1 at the same time allows a 16-bit data transfer.

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For proper bus alignment in the 16-bit mode, the low order byte (D0 - D7) must be located at an odd address. The high order byte (D8 - D15) must be located at an even address.

4.3.1 A0 - A15 (pin 2a to 9a and 2b to 9b) - Applicable to G-64. - Address bus: Tri-state signals, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module). These 16 signals are used to specify the source or destination address or a data transfer. The address specified in a 16-bit data system is a word address. 4.3.2 A0 - A23 (pin 2a to 9a, 2b to 9b and 2c to 9c) - Applicable to G-96. - Address bus: Tri-state signals, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module). These 24 signals are used to specify the source or destination address of a data transfer. The address specified in a 16-bit data system is a word address.

4.3.2 A0 - A31 (pin 2a to 9a, 2b to 9b, 2c to 9c and 2d to 9d) - Applicable to G-96+. - Address bus: Tri-state signals, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module).

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These 24 signals are used to specify the source or destination address of a data transfer. For 32-bit data transfert, 16 of these lines (A0 – A15) are multiplexed and used to transfer the additional 16 databits. D16-D31. More details on the 32-bit mode is given in chapter 5. These address lines always specify a word address.

4.4

Page (pin 27a)

- Applicable to G-64, G-96 . - Address line: Tri-state signal, 48 mA - Origin: Bus Master (CPU module) or Bus Requester (DMA module). This signal, when asserted, specifies together with A0 to A 15 or A0 to A23 an address in the page 0. At the high level, the address is specified in the page 1. The Page signal can be used as an address extension to double the addressing capability of the bus.

4.5

DS0 , DS1 (pin 11a and 11b) - Applicable to G-64, G-96. - Data strobe: Tri-state signal, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module).

DS0 is used to signal transfer of the low order byte (D0 -D7) and DS1 of the high order byte (D8 -D15). Note that DS0 and DS1 should not be used in 8-bit microprocessor systems.

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4.6

VMA (pin 16a)

- Applicable to G-64, G-96, G-96+. - Valid Memory Address: Tri-state signal, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module). This signal, when asserted, indicates that the address specified by the address bus and Page is valid and located in the Memory field. The falling edge of VMA is used to indicate the beginning of a memory Read/Write cycle.

4.7

VPA (pin 14a)

- Applicable to G-64, G-96, G-96+ - Valid Peripheral address: Tri-state signal, 48 mA. - Origin: Bus Master (CPU module). This signal, when asserted, indicates that the address specified by A0 to A9 is valid and located in the Peripheral field. The size of the Peripheral field is 1 Kbyte/Kword (10-bit address). The falling edge of the VPA signal is used to indicated the beginning of the peripheral Read/Write cycle. The VPA signal simplifies and reduces the decoding logic of the I/O modules. The VPA field is generally decoded in the total address range of the CPU module. Some processors provide their own validation signal for the I/O which can be used directly to drive the VPA bus signal. However, These processors generally use only 8 address lines (256 I/O), thus addresses A8 and A9 are not specified and it is recommended to force them to the high level during an I/O cycle.

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4.8

BRQ (pin 10b)

- Applicable to G-64, G-96, G-96+ - Bus Request: Open collector signal 48 mA. - Origin: Bus Requester (DMA module). This signal, when asserted, indicates to the Bus Master (CPU module) that a Bus Requester requires the bus for a DMA transfer. BRQ can be released shortly after the assertion by the bus requester of the BBUSY signal.

4.9

BGRT (pin 10a)

- Applicable to G-64, G-96, G-96+. - Bus Request: Open collector signal 48 mA. - Origin: Bus Master (CPU module). This signal, when asserted, indicates to bus Requester that the bus is available for DMA transfer. Note: BGRT can be released during the DMA transfer after BBUSY is asserted and BRQ is no longer asserted (Applicable only with processor modules implementing the BBUSY function-typically most 16/32-bit microprocessor modules). The Chain in and Chain Out signals (CHIN-CHOUT) should be used to set up priority when there is more than one Bus Requester (see also 4.16). BGRT and IACK are exclusive signals and will never be asserted together. The arbitration between a Bus request and an Interrupt request is made in a processor itself, on the CPU module, which gives an exclusive BGRT or IACK response.

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4.10

BBUSY (pin 12b)

- Applicable to G-64, G-96, G-96+. - Bus Busy: Open collector signal 48 mA. - Origin: Bus Master (CPU Module) or Bus Requester (DMA module). BBUSY indicates that the bus is currently used by Bus Master (CPU module) or a bus requester (DMA module). BBUSY remains low for the duration of a transaction which can stretch over several transfers. The signal BBUSY is active low and wired-ored to the bus. When the signal BBUSY is asserted by a Bus Requester, its BRQ signal can be removed.

4.11

IRQ5 , IRQ3 (pin 17c and 16c)

- Applicable to G-96, G-96+. - Interrupt Request Level 5 and 3: Open collector signal, 48 mA. - Origin: Interrupt Requester (I/O module) This signal, when asserted, requires an interrupt sequence from the Bus Master. The I/O device asserts the interrupt line as long as it is not serviced. The priorities are listed in the ascending mode (IRQ5 = highest, IRQ1 = lowest). These interrupt lines are level sensitive.

4.12

IRQ1 , IRQ2 , IRQ4 (pin 16b, 17b and 18a)

- Applicable to G-64, G-96, G-96+. - Interrupt Request Level 1,2 and 4: Open collector signal, 48 mA. - Origin: Interrupt Requester (I/O module).

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This signal when asserted requires an interrupt sequence from the Bus Master The I/O device asserts the interrupt line as long as it is not serviced. The priorities are listed in the ascending mode (IRQ5 = highest, IRQ1 = lowest). These interrupt lines are level sensitive.

4.13

NMI (pin 15b)

- Applicable to G-64, G-96, G-96+. - Non Maskable interrupt: Open collector signal, 46 mA. - Origin: Interrupt Requester (I/O module). This is signal when asserted requires an interrupt sequence from the Bus Master. This interrupt is not maskable and cannot be vectored. NMI is falling edge sensitive.

4.14

PWF (pin 29a)

- Applicable to G-64, G-96, G-96+. - Power-fail detect : Open collector signal, 48 mA. - Origin: Power Supply Supervisor. This signal when asserted indicates of an imminent loss of power to the system. This signal is treated as a Non Maskable Interrupt by the CPU module(s). This line falling edge and low level sensitive. 4.15

IACK (pin 18b)

- Applicable to G-64, G-96, G-96+. - Interrupt Acknowledge: Tri-state signal, 48 mA. - Origin: Bus Master (CPU module). 31

This signal, when asserted, indicates that the Bus Master is responding to an interrupt request and expecting a vector to be placed on the data bus line D0 to D7. This signal is not activated when the CPU module does not treat the incoming interrupt as a vectored interrupt (auto-vector mode). In this case, the source of the interrupt is found using software polling technique. When interrupt vectors are used, the CHIN , CHOUT and IACK signals must be used to determine priority between different I/O modules which generate interrupts of the same level. This will cause the module closest to the CPU module to be the only to emit the interrupt vector. In order to know at which interrupt level the CPU module is responding, the address lines A0 to A2 are used to encode one of the 5 interrupt levels at which the CPU module is responding when asserting the IACK signal. BGRT and IACK are exclusive signals and will never be asserted together. The arbitration between a Bus request and an interrupt request is made in the processor itself, on the CPU module, which gives an exclusive BGRT or IACK response.

4.16

CHIN, CHOUT (pin 28b, 28a)

- Applicable to G-64, G-96, G-96+. - Daisy chain: Totem pole signals, 8 mA. - Origin: Bus Master or first module involved in the chain. These two signals are used to build a daisy chain to resolve contention between modules in a group of Bus Requesters (DMA modules) and/or Interrupt Requesters (I/O modules).

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The first module in a chain must be supplied with a pull-up resistor on its CHIN pin. If this condition is not respected, this module must be plugged into the adjacent connector of the of the CPU module which has a pull-up resistor on its CHOUT pin. Priority can be set up for two separated groups of modules using the daisy chain. These two groups are interrupt and Bus requesters. The modules in a group must be placed in adjacent connectors with eventual empty positions having their CHIN and CHOUT signals short-circuited.

4.17

BERR (pin 27b)

- Applicable to G-64, G-96, G-96+. - Bus error: Open collector signal 48 mA. - Origin: Addressed device (memory or peripheral). This signal, when asserted, indicates to the Bus Master that an error occurred during a data transfer or that the information read from a memory module has a parity error.

4.18

ENABLE (pin 13b)

- Applicable to G-64, G-96, G-96+. - Synchronous clock: Totem pole or tri-state, 48 mA. - Origin: Bus Master (CPU module). This signal is used by synchronous devices to enable data transfer. The tristate capability is optionally selectable. All signals in a synchronous transaction are referred to the Enable signal.

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Enable signal is also used to refresh dynamic devices or memory and thus it should not be interrupted for a period exceeding the timing specifications.

4.19

SYCLK (pin 13a)

- Applicable to G-64, G-96, G-96+. - System clock: Totem pole or tri-state,48 mA - Origin: SYCLK is generally issued from the Bus Master . This signal, is general purpose clock which has no imposed frequency and timing relationship to the other signals in the G-64 specification except for the maximum frequency allowed. In synchronous systems the SYCLK be a copy of the Enable signal. In asynchronous systems, the SYCLK will generally be a copy of the CPU clock. A board designed for a asynchronous systems should be able to work without the need of SYCLK. However SYCLK can be used optionally to increase the performance of modules like dynamic RAM which can be synchronized with the CPU clock for more efficient operation. There is no protocol for the SYCLK signal, thus it must be selectable and specified for each module from which it can be issued.

4.20

R/W (pin 17a)

- Applicable to G-64, G-96, G-96/32 and G96/64. - Read/Write: Tri-state signal, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module). This signal defines a read cycle at the high level and a write cycle at the low level. Data direction is given by the R/W signal. During the read cycle (R/W 34

at he high level) data flow from the addressed device to the Bus Master of DMA module in use, which generates the address and control signals. In the write mode (R/W at low level), address control signals are issued from the Bus Master or DMA module and data flow to the addressed device.

4.21

RDY or DTACK (pin 15a)

- Applicable to G-64 (RDY) - Applicable to G-64, G-96, G-96+ (DTACK) - Ready / Data Acknowledge: Open collector signal, 48 mA - Origin: Addressed device (memory or peripheral). This signal is used in two different ways following the synchronous or asynchronous mode. Synchronous mode (RDY): In a synchronous system, this signal can be used by slow memory or peripheral devices. It is tied low during a data transaction to force the CPU module to add wait states. The Enable signal period must not exceed the specified timing limit. Therefore, the RDY must not be held too long at the low level. Generally, the modules in a synchronous system are built with devices which operate without additional wait states and the RDY line is not used (high level). Asynchronous mode (DTACK): In the asynchronous mode, this signal is used in all data transactions which are read/write memory or peripheral and read vector in an interrupt acknowledge cycle. The DTACK signal, when asserted indicates for the Bus Master or DMA module that valid data is available on the bus during a read cycle or data has been accepted from the bus during a write cycle. DTACK is the handshaking signal used in the asynchronous mode.

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When a cycle initiated by the VMA, VPA or IACK signal is not acknowledged by asserting DTACK within a predefined delay period, the CPU module must be able to abort this cycle and resume operation.

4.22

HALT (pin 12a)

- Applicable to G-64, G-96, G-96+ - Halt Processor; Open Collector signal, 48 mA. - Origin: peripheral modules. This signal, when asserted will stop all activity in the CPU module, HALT can be asserted for an indefinite time. When in halt, the Bus Master will put al l tri-state output lines, in high impedance state.

4.23

RESET (pin 14b)

- Applicable to G-64, G-96, G-96+ - Reset: Open collector signal, 48 mA. - Origin: Bus Master (CPU module) or peripheral modules. Generally the RESET signal is issued from the CPU module after power-on or by depressing the reset switch. The RESET signal can also be generated by any module on the bus. The RESET signal is bi-directional and should be an output as well as an input to the CPU module. Its action is to initialize the complete system.

4.24

SYSFAIL (pin 27c)

- Applicable to G-64, G-96, G-96/32 and G96/64. - System Fail: Open collector signal, 48 mA. - Origin: Bus Master (CPU Module) or peripheral modules. 36

The SYSFAIL signal is reset after the system RESET or power-on. This signal must then be set high by each bus master on the bus, usually after successful completion of self test program. If SYSFAIL is to remain low after a predefined time, it indicates that one or more CPU modules in the bus are defective. SYSFAIL can also go low during system operation to indicate that one of the bus master has become defective. This can be achieved by having this signal associated with a watch dog circuitry on the bus masters. SYSFAIL is implemented in order to provide superior fault tolerance to the system.

4.25

P0 -P5 (pin 25c-20c)

- Applicable to multi-processor G-96, G-96+ - Priority of Multi-Master Bus Request: Open collector signal, 48 mA. - Origin: Bus Master (CPU module) in multi-processor configuration. P0 to P5 are used to encode the current priority (1 to 31) of the Bus Master and used to resolve contention between several Bus Requesters in a multimaster environment. These lines are wired-ored on the bus to allow parallel arbitration with the priority of other modules competing for control of the bus. More details on this arbitration mechanism is given in chapter 6.

4.26

VED (pin 18c)

- Applicable to multi-processor G-96, G-96+ - Valid Event Data: Tri-state signal, 48 mA. - Origin: Bus Master (CPU Module) in multi-processor configuration. VED is used to synchronize transfer of message between. Bus Masters. An Event message transfer is initiated by the VED signal asserted low.

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VED remains low for the entire duration of the message transfer. Each data word is validated by a low level on the DS0 and DS1 lines. The Event Receiver module(s) acknowledge each data word with the DTACK (successful transfer) signal of BERR signal (unsuccessful transfer). When VED is asserted., the VMA and VPA signals are released (high level) and R/W line is in the write mode.

4.27

BWD (pin 10c)

- Applicable to multi-processor G-96, G-96+ - Bus Wanted: Open collector signal, 48 mA. - Origin: Bus Master (CPU Module) in multi-processor configuration. This signal, when asserted, indicates to the current Bus Master that another Bus Master wants to take control of the bus. The falling edge of the BWD initiates the bus arbitration procedure. Note that BWD is released only after the new master has taken control of the bus and asserted the BBUSY line.

4.28

BARB (pin 12c)

- Applicable to multi-processor G-96, G-96+ - Bus Arbitration: Open collector signal 48 mA. - Origin: Bus Master (CPU Module) in multi-processor configuration. BARB is used to a signal that the bus is currently undergoing a multi-master bus arbitration resolution. This wired-ored line is activated at the same time as the BWD. BARD will return to a high level after the arbitration has been resolved and a new master has won the bus.

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4.29

LWORD (pin 11c)

- Applicable to G-96+. - Long Word Data: Tri-state signal, 48 mA. - Origin: Bus Master (CPU module) or Bus Requester (DMA module). LWORD is used to signal the transfer of the long word (D0 - D31) on the bus. For proper byte alignment, this is always used in association with the DS0 and DS1 data strobes and the address line A0.

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CHAPTER 5 DYNAMIC OPERATIONS 5.1 INTRODUCTION Most of G-64 Bus signals are used for both synchronous or asynchronous transfer. Read, write, interrupt and bus request operations will be discussed both for synchronous and asynchronous operations. 5.2 SYMBOLS USED IN TIMING DIAGRAM Dynamic characteristics that are defined in this manual refer to the G-64 Bus signals as they appear on the backplane. Symbols used in the timing are illustrated in fig. 5.1.

Fig. 5.1 Signal symbols.

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5.3 SYNCHRONOUS OPERATION

5.3.1 INTRODUCTION The synchronous mode is well adapted to interface 8-bit processor, memory and peripheral modules. The paragraphs below discuss the timing and the signals used for different transactions in the synchronous mode. When using a 16 or 32-bit processor, all data transfer should be made in the asynchronous mode. When performing 8-bit peripheral data transfer on D0 D7.

5.3.1 READ-WRITE OPERATION Read/write cycle is used in memory and peripheral addressing. A read operation is used in the interrupt acknowledge cycle to pass a vector on D0 D7 data lines when using vectored interrupt features.

5.3.3 MEMORY AND I/O READ/WRITE CYCLE Fig. 5.2 illustrates the G-64 reference timing for memory and peripheral read or write cycles. This timing is used to build G-64 compatible modules, CPU and DMA boards.

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1 2 3 4 5 6

Cycle time Enable low Enable high Hold time Address and Page set-up time VMA/VPA command time lead time

7 VMA/VPA inactive 8 Read or Write command lead time 9 Write data set-up time 10 Read data access time 11 Write data high impedance hold time 12 Read data high impedance hold time

* For peripheral only addresses A0-A9 are used with the VPA Note: all values are in [ns]. Fig. 5.2 Memory and I/O synchronous read/write cycles 43

5.3.5 SLOW DEVICE CYCLE The RDY signal allows slow devices to interface with the G-64 bus. The effect of RDY when negated is to add wait states in a transfer cycle. RDY can affect only memory and peripheral cycles. The processor devices have different ways to generate ways states from one manufacturer to another. The modules designed to be compatible with the G-64 bus must respect the timing of fig. 5.3 below. The relation between RDY signal and the additional wait states is not specified since it can be different from one module to another but the maximum period for the Enable signal must be respected.

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1 Cycle time 2 Enable low 3 Enable high 4 RDY negated delay * These signals cannot be asserted at he same time. Note: - 5 is not specified but 1 must be respected 6 All values in [ns] Fig. 5.3 Slow cycle - synchronous mode

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5.4 16-BIT ASYNCHRONOUS OPERATION 5.4.1 INTRODUCTION The asynchronous mode in the G-64 bus is generally used in 16-bit and 32bit systems. They are intended to be of high performance and speed. Asynchronous transfer allows bus cycles of less than 1µs (100ns min.) Simple peripheral modules can be addressed following the G-64 synchronous timing in order to maintain compatibility. The synchronous transfers for I/O modules are made on 8-bit data. The performance of I/O modules may be increased if they operate in the asynchronous mode. The address fields must be selectable individually to operate both in the synchronous and asynchronous mode. The I/O field selected in the asynchronous mode will be addressed in the same way as asynchronous memory and the VPA signal must follow the same timing as VMA.

5.4.2 16-BIT BUS ALIGNMENT The smallest addressable unit of storage on the G-64 bus is the byte location. Each byte location is assigned a unique binary address. Each byte location can be either the most significant byte (even byte address) or the least significant byte (odd byte address) of the 16-bit word. The bus address line A0 to A23 are used to select which two-byte (word) group will be accessed. Two additional lines DS0 and DS1 is, then used to select which byte location within the two-byte group are accessed during the data transfer. Using these two lines, a processor module or bus requester (DMA) can access one or two byte locations simultaneously: Fig 5.4 shows bus alignment in the 16-bit mode.

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Note: DS1 selects the even byte D8 - D15 DS0 selects the odd byte D0 - D7

Fig. 5.4 16 bit bus alignment scheme

Note: The A0 to A23 on the G-64 bus is word address. Microprocessor using A0 to An to define byte address need to have all address lines shifted so that A1 on the microprocessor become A0 on the bus.

5.4.2 READ-WRITE OPERATION Read, write or read-modify cycles in the asynchronous mode must be operational with all memory boards and peripheral modules having asynchronous transfer capability. A read operation is used in the interrupt acknowledge cycle to pass a vector on data lines D0 - D7 when using the vectored interrupt feature.

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5.4.3 MEMORY AND I/O WRITE CYCLE The timing used for a write cycle is illustrated on fig. 5.5. A memory cycle is validated by asserting VMA, while addressing a peripheral is performed by asserting VPA. The cycle is terminated by the assertion of either the DTACK or BERR signal to inform the processor module of the successful or unsuccessful completion of the write cycle.

Fig. 5.5 Asynchronous write cycle

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1 Address set-up time 2 Address hold time 3 VMA or VPA high (inactive) 4 VMA or VPA low to DSx low delay 5 DSx high (inactive) 6 DSx high to VMA or VPA high lead time 7 DSx to DSy skew 8 DSy high (inactive) 9 DSy high to VMA or VPA high lead time 10 Write command set-up time 11 Write command hold time 12 Data set-up time 13 Data hold time 14 DSy low to DTACK low delay 15 DTACK low to DSx high delay 16 DSy high to DTACK high delay 17 DTACK high to VMA or VPA low lead time Notes: * DSx and DSy are represented to show the timing relation between the 2 data strobes. DSx represents DS0 if DSy represents DS1 and vice-versa. 7 All signals represented are issued from the Bus Masters except the handshaking signal DTACK, issued from the addressed slave module, which indicates that the data has been accepted and the cycle can terminate. 8 VMA and VPA have the same timing. VMA is activated for memory and VPA for peripheral addressing. 9 All values are in [ns].

Fig. 5.5 Asynchronous write cycle

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5.4.4 MEMORY AND I/O READ CYCLE The timing used for a read cycle is illustrated in Fig. 5.6. A memory cycle is validated by asserting VMA, while addressing a peripheral is performed by asserting VPA. The cycle is terminated by the assertion of either the DTACK or BERR signal to inform the processor module of the successful or unsuccessful completion of the read cycle.

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Fig. 5.6 Asynchronous read cycle 1 Address set-up time 2 Address hold time 3 VMA or VPA high (inactive) 4 VMA or VPA low to DSx low delay 5 DSx high (inactive) 6 DSx high to VMA or VPA high lead time 7 DSx to DSy skew 8 DSy high (inactive) 9 DSy high to VMA or VPA high lead time 10 Read command set-up time 11 Read command hold time 12 Data set-up time 13 DSx low to Data Bus ON 14 Data hold time 15 DSy high to Data Bus OFF 16 DSy high to DTACK high delay 17 DTACK high to VMA or VPA low lead time Notes: *DSx and DSy are represented to show the timing relation between the 2 data strobes. DSx represents DS0 if DSy represents DS1 and vice-versa. - All signals represented are issued from the Bus Master except D0-D15 and the handshaking signal DTACK issued from the addressed slave module, which indicates that the Data are valid and the cycle can terminate. 10 VMA and VPA have the same timing. VMA is activated for memory and VPA for peripheral addressing. 11 All values are in [ns].

Fig. 5.6 Asynchronous read cycle

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5.4.5 READ-MODIFY-WRITE CYCLE (RMW) The RMW cycle is indivisible and is performed by asserting VMA throughout the entire cycle with the address unchanged. The other signals respect the timing of the normal read followed by a normal write cycle. The timing used for a RMW cycle is illustrated in fig. 5.7.

Fig. 5.7 Asynchronous read-modify-write cycle

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1 Address set-up time 2 Address hold time 3 VMA or VPA high (inactive) 4 VMA or VPA low to DSx low delay 5 DSx high (inactive) 6 DSx high to VMA or VPA high lead time 7 DSx to DSy skew 8 DSy high (inactive) 9 DSy high to VMA or VPA head lead time 10 Read command set-up time 11 Read command hold time 12 Data set-up time 13 DSx low to Data Bus ON 14 Data hold time 15 DSy high to Data Bus OFF 16 DSy high to DTACK high delay 17 DTACK high to DSx low lead time 20 Write command set-up time 21 Write command hold time 22 Data set-up time 23 Data hold time 24 DSy low to DTACK low delay 25 DTACK low to DSx high delay 26 DSy high to DTACK high delay 27 DTACK high to VMA or VPA low lead time

Notes: - 1 to 16 are the same parameters and timing as 1 to 16 in the read cycle of fig 5.6. - 20 to 27 are the same parameters and timing as 10 to 17 in the write cycle of fig 5.5. - DSx and DSy are represented to show the timing relation between the 2 data strobes. - DSx represents DS0 if DSy represents DS1 and vice-versa. - All values are in [ns]. Fig. 5.7 Asynchronous read-modify-write cycle

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5.5 32-BIT ASYNCHRONOUS OPERATION 5.5.1 INTRODUCTION The G-64 bus supports full 32-bit data transfer. This extension to the original bus specification uses a multiplexing scheme where the address lines A0 to A15 are dynamically shared with data lines D16 to D31. This 32-bit mode is designed in such a way that it permits total and transparent upward compatibility with older 8 or 16-bit G-64 I/O modules. The 32-bit mode requires that memory modules in the bus are designed to handle 32-bit data transfer. All G-96+ compatible products can be identified by this logo:

5.5.2 32-BIT BUS ALIGNMENT The smallest addressable unit of storage on the G-64 bus is the byte location. Each byte location is assigned a unique binary address. Each byte location can be one of the four bytes that make 32-bit word. The bus address lines A1 to A23 are used to select which four-byte (longword) group will be accessed. Four additional lines LWORD, DSO, DS1, and A0 are then used to select which byte locations within the four-byte group are accessed during the data transfer. Using these four lines, a processor module or bus requester (DMA) can access one, two, three or four byte locations simultaneously. Note that in the absence of the LWORD

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signal, the bus automatically reverts to 16-bit mode. This allows 16-bit bus requesters (DMA) to access all possible locations on a 32-bit memory module. Fig. 5.8 allows the various combinations of these four signals and the resulting bus alignment.

Fig. 5.8 32-bit bus alignment scheme

Note: The A0 to A23 on the G-64 bus is a word address: Microprocessor using A0 to An to define byte address need to have all address lines shifted so that A1 on the microprocessor becomes A0 on the bus.

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5.5.3 32-BIT MEMORY WRITE CYCLE The timing used for a write cycle is illustrated on the fig. 5.9. A 32-bit memory cycle is validated by asserting VMA. Memory modules can use the falling edge of the VMA signal in order to latch the address lines A0 to A15. The cycle is terminated by the assertion of either the DTACK or BERR signal to inform the processor module of the successful or unsuccessful completion of the write cycle.

Fig. 5.9 Asynchronous write cycle

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1 Address set-up time 2 Address (A0-A15) hold time 3 VMA low to DSxy low delay 4 R/W and LWORD set-up time 5 Data set-up time 6 DSxy high to VMA high lead time 7 R/W and LWORD hold time 8 Data hold time 9 DSxy low to DTACK low delay 10 DSxy high to DTACK high delay 11 Address (A16-A23) hold time 12 VMA high inactive 13 DTACK high to next bus cycle lead time

Notes: *DSxy is represented to show the timing relation of the 2 data strobes (DS0, DS1). - All signals represented are issued from the Bus Master except the handshaking signal DTACK issued from the addressed slave module, which indicates that the Data have been accepted and the cycle can terminate - All values are in [ns].

Fig. 5.9 Asynchronous write cycle

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5.5.4 32-BIT MEMORY READ CYCLE The timing used for a read cycle is illustrated in fig. 5.10. A 32-bit memory cycle is validated by asserting VMA. Memory modules can use the falling edge of the VMA signal in order to latch the address on address lines A0 to A15. The cycle is terminated by the assertion of either the DTACK or BERR signal to inform the processor module of the successful or unsuccessful completion of the read cycle.

Fig. 5.10 Asynchronous read cycle

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1 Address set-up time 2 Address (A0-A15) hold time 3 VMA low to DSxy low delay 4 R/W and LWORD set-up time 5 Data bus OFF to DSxy low 6 DSxy high to VMA high lead time 7 R/W and LWORD hold time 8 Data hold time, bus OFF 9 Data set-up time to DTACK low 10 DSxy high to DTACK high delay 11 Address (A16-A23) hold time 12 VMA high (inactive) 13 DTACK high to next bus cycle lead time

Notes: *DSxy is represented to show the timing relation of the 2 data strobes (DS0, DS1). - All signals represented are issued from the Bus Master except D0 - D31 and the handshaking signal DTACK issued from the addressed slave module, which indicates that the Data are valid and the cycle can terminate. - All values are in [ns].

Fig. 5.10 Asynchronous read cycle

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5.5.5 32-BIT READ-MODIFY-WRITE CYCLE (RMW) The RMW cycle is indivisible and is performed by asserting VMA throughout the entire cycle with the address unchanged. The other signals respect the timing of a normal read followed by a normal write cycle. The timing used for a RMW cycle is illustrated in fig. 5.11. Note that the RMW cycle cannot be performed on misaligned data boundaries.

Fig. 5.11 Asynchronous read-modify-write cycle 60

1 Address set-up time 2 Address (A0-A15) hold time 3 VMA low to DSxy low delay 4 R/W and LWORD set-up time 5 Data bus OFF to DSxy low 6 DSxy high to VMA high lead time 7 R/W and LWORD hold time 8 Data hold time, bus OFF 9 Data set-up time to DTACK low 10 DSxy high to DTACK high delay 11 DTACK high to DSxy low lead time 12 VMA high (inactive) 13 DSxy high (inactive) 14 R/W and LWORD set-up time 15 Data set-up time 16 Address (A16-A23) hold time 17 R/W and LWORD hold time 18 Data hold time 19 DSxy low to DTACK low delay 20 DSxy high to DTACK high delay 21 DTACK high to next bus cycle lead time

Notes: - DSxy is represented to show the timing relation of the 2 data strobes (DS0, DS1). - All values are in [ns].

Fig. 5.11 Asynchronous read-modify-write cycle

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5.6 INTERRUPTS 5.6.1 INTRODUCTION In a single processor system, there is only one processor which receives the interrupt requests from its I/O devices. The processor is usually located on one card while the peripherals are located on the other cards. The whole is interconnected by the G-64 bus which carries the interrupt requests from the devices to the processor. Interrupt request lines are selectable to be vectored or non-vectored (autovectored) interrupts. They are level sensitive and allow several interrupt sources to be connected on the same line. Interrupt request lines must remain active until cleared by the software interrupt routine. 5.6.2 AUTO-VECTORED INTERRUPTS In this mode, an interrupting module asserts one of the 6 interrupt lines on the bus. The processor module responds to this interrupt request by executing a service routine and no further exchange of interrupt related signal occurs on the bus. The processor needs to use a software polling techniques in order to identify the interrupt source(s). The auto-vectored mode is a function of the hardware on the processor module. 5.6.3 VECTORED INTERRUPTS In the vectored interrupt mode, when one or more I/O devices generate an interrupt request., the processor services the interrupt during the interrupt acknowledge operation. During an interrupt acknowledge the CPU module reads an 8-bit vector on the data bus. That vector allows the processor on the CPU module to branch to the specific interrupt routine. A vector read cycle is similar to a memory cycle. The IACK signal validates the cycle with the vector placed on a data lines D0 - D7. When IACK is asserted, VMA and VPA are disabled and R/W is in the read mode. The contention between several interrupt requesters is resolved by a daisy-chain structure.

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5.6.4 SYNCHRONOUS INTERRUPT VECTOR READ CYCLE A vector read cycle is similar to a memory cycle. The IACK signal validates the cycle with the vector placed on data lines D0 - D7. When IACK is asserted, VMA and VPA are negated and R/W is in the read mode. The IACK cycle with vector read is illustrated in fig 5.12. next page.

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1 2 3 4 5

Cycle time Enable low Enable high Enable to IACK, invalid time IACK valid time

6 IACK lead time 7 Enable low to IACK negated 8 Vector access time 9 Vector hold time 10 Interrupt level - address set-up time 11 Interrupt level - address hold time

Notes: - The CPU module must generate an IACK pulse with respect to the timing proposed here and satisfy its own requirements. - *A0 to A2 indicate the interrupt level at which the Bus Master is responding. If more than 1 line operates in the vectored interrupt mode. - All values in [ns].

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Fig. 5.12 IACK synchronous cycle 5.6.5 ASYNCHRONOUS INTERRUPT VECTOR READ CYCLE The vector read cycle is similar to a memory read with IACK signal asserted for a single cycle. During this cycle VMA and VPA are at a high level and the data strobes are not used. The cycle is terminated by the assertion of DTACK signal. Fig. 5.13 illustrates the IACK bus cycle on next page.

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1 2 3 4 5 6

Address set-up time Address hold time Read command set-up time Read command hold time Last cycle to IACK valid delay IACK high to VMA or VPA low (next cycle delay)

7 IACK low to Data Bus OFF 8 Data set-up time 9 Data hold time 10 IACK high to Data Bus released 11 IACK high to DTACK high delay 12 DTACK high to VMA or VPA low (next cycle) lead time

Notes: - All signals are issued from the Bus Master except the interrupt vector D0 - D7 and the handshaking signal DTACK, issued from the addressed slave module, which indicates that the interrupt vector is valid and the cycle can terminate. - A0 - A2 indicate the interrupt level at which the Bus Master is responding. - D8 to D15 are not used in the IACK cycle. - All values are in [ns].

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Fig. 5.13 IACK asynchronous cycle 5.6.6 NON MASKABLE INTERRUPT NMI is the non-maskable interrupt line and should have a single interrupt source. This signal is negative edge sensitive but must be asserted (low level) until it is cleared by the interrupt service routine. However, this interrupt is recognized immediately by most processor modules and needs generally to be active for a single cycle. Fig. 5.14 and 5.15 show the timing for NMI in the synchronous and asynchronous mode respectively.

Fig. 5.14 Single cycle NMI - synchronous mode

Fig. 5.15 Single cycle NMI - asynchronous mode

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5.6.7 POWER FAIL This signal is asserted by the power supply supervisor in order to indicate the imminent loss of power to the system. This signal is treated as a NonMaskable interrupt by the CPU module(s). This line is falling edge and low level sensitive. This signal must detect power loss far enough in advance to permit the processor(s) to take preventive action prior to the total loss of power. Fig. 5.16 illustrates the timing diagram of the power fail interrupt.

Fig. 5.16 Power fail interrupt timing

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5.7 BUS ERROR The BERR signal is used to indicate the processor module performing an asynchronous data transfer that an error has occurred. Typically, the BERR signal is issued from a memory or peripheral module. For example, a memory module can indicate a Parity error by asserting BERR. In this case BERR should have the same timing as DTACK which would be asserted if no error had occurred. To avoid having a processor module wait for a non-responding device in an asynchronous data transfer, a time-out circuitry must issue bus error signal (BERR asserted internally to the processor module) after internal time out (typically 8 µs). By asserting BERR the cycle must be aborted and operation may continue. Fig 5.17 illustrates the timing of BERR which allows supervision of an asynchronous cycle.

Fig. 5.17 BERR timing

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5.8 BUS SHARE The bus can be shared by the CPU module and one or more DMA modules. The daisy chain is required to resolve contentions when more than one DMA module request the bus. Daisy chain principle is discussed in chapter 5.9. The timing used for one or more asynchronous DMA modules sharing the bus with the CPU is illustrated on fig. 5.18

1 BRQ is asserted asynchronous by the DMA requester 2 BGRT is asserted by the CPU module 3 BBUSY is asserted if VMA, VPA and DTACK are negated 4 DMA transfer can take place after BBUSY is asserted 5 BRQ can be negated after BBUSY is asserted 6 The CPU module can negate BGRT after BRQ is negate 7 DMA transfer completed: BBUSY is negated if VMA, VPA and DTACK are negated. Note: all values are in [ns]. Fig. 5.18 DMA bus request timing - asynchronous mode

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5.9 DAISY CHAIN

5.9.1 DAISY GENERAL INFORMATION The daisy chain is used to set up priority between several vectored interrupt sources or DMA modules. All modules using this feature are plugged into adjacent connectors to form a group with a continuous daisy chain. At least, the first module in the chain is supplied with a pull-up resistor to start the chain. Fig. 5.19 shows such a daisy chain arrangement of boards in a G-64 bus system.

Fig. 5.19 Module arrangement for use of daisy chain

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5.10.2 DAISY CHAIN CIRCUIT FOR INTERRUPTS Fig. 5.21 below shows a block diagram of the circuitry needed to implement priority between vectored interrupt sources on the daisy chain. The comparator allows identification of the interrupt level when more than one line is used for vectored interrupt. This comparator is not necessary when vectored interrupts are implemented on a single level, but in this case, the IACK signal must be valid only for this level. The DTACK signal is used when the vector read operation is made in the asynchronous mode (asynchronous systems), but must be deselected for the synchronous transfer mode. This circuitry is usually required and implemented in all G-64 bus products using vectored interrupts. GESPAC offers a custom IC that implements all these functions. Fig. 5.20 shows a practical implementation of that IC.

Fig. 5.20 Daisy chain circuitry for interrupts

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Fig. 5.21 Practical implementation using GESPAC interrupt handler IC

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5.9.3 DAISY CHAIN CIRCUIT FOR BUS REQUESTS Fig. 5.22 below illustrates a complete circuit which can be used to implement priority between DMA modules on the daisy chain.

Fig. 5.22 Daisy chain circuitry for bus requesters (DMA)

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5.9.4 DAISY CHAIN TIMING An example of a daisy chain resolution cycle is shown on fig. 5.24. This example assumes that there are four modules in the chain and device number 3 generates an interrupt or DMA request. When IACK or BGRT goes low, all boards in the chain will assert their CHOUT line at the low level for predefined arbitration period. After that delay, modules begin releasing their CHOUT line. The chain is propagated from one module to the next until it reaches the requester module that will lock the chain, thus disabling all following modules in the chain.

1 BGRT/IACK low to all CHOUT low delay 2 All CHOUT must be asserted or the arbitration duration 3 CHOUT is released if the I/O module has no request pending 4 CHOUT is kept low if the current I/O module has a request pending 5 BGRT/IACK high to all CHOUT high delay Note: all values are in [ns] Fig. 5.23 Daisy chain timing example

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5.10 SYSTEM RESET The reset signal RESET is used to initialize the complete system. This signal is asserted during the power up and power down operations. It may also be asserted when the system is powered to reinitialize it completely, an action which is generally initiated by depressing a push button switch. Reset during power up and down is illustrated in fig. 5.25. The RESET signal must be asserted for a minimum of 200 ms in all cased including the reset operation on a powered system.

Fig. 5.25 Power up/down reset

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5.11 SYSTEM CLOCK The system clock is limited to 10 MHz on a two layer printed circuit backplane. Frequencies up to 20 MHz are acceptable on multi-layer terminated backplanes. The system clock signal is illustrated in fig. 5.26. This clock signal is provided on the bus by the processor module as a general-purpose clock signal. Frequency of this signal is not dictated by specification. This signal does not have any specified timing relationship with any other bus signals.

Fig. 5.26 SYCLK - system clock timing

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CHAPTER 6 MULTI-PROCESSOR MODE

6.1 INTRODUCTION Multi-processor permits to achieve higher system performance by sharing to work load amongst several processors running concurrently in this bus. This portion of the bus specification describes how to implement a decentralized multiple processor architecture capable of supporting up to 31 masters on the G-64 bus. This extension to the specification is designed in such a way to ensure total upward compatibility with less sophisticated memory and I/O modules. When not specified, the multi-processor timings comply with the 16-bit and 32-bit asynchronous timing described in the previous chapter of this manual. The multi-processor extension does not allow the mix in the same backplane of single-processor and multi-processor CPU modules. The specification supports all existing peripheral modules including those capable of DMA. All existing memory modules are fully compatible with this specification. The multi-processor specification introduces the concept of message passing to the G-64 bus. Message passing allows very fast inter processor communication and is the key to efficient multi-processor systems. Events, a special form of message, can be used to replace hardware interrupts when an interrupting device needs to direct the interrupt to a particular processor in the bus.

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6.2 ARBITRATION 6.2.1 ARBITRATION DESCRIPTION The arbitration resolves contention between up to 31 Bus Masters by means of a distributed (or decentralized) arbitration logic. When multiple processors compete for control of the bus, the arbitration designates one and only one winner which becomes the master of the bus, normally for the duration of one transfer. In a distributed arbitration system, each possible Bus Master module contains its own arbitration logic and has a unique number which defines its priority level on the bus. This configuration presents the following advantages: The priority level is directly select by jumpers on the Bus Master module. In this way, the priority is independent of the relative position. of the module in the backplane. Moreover, the replacement of a defective module is easier. The priority level is directly known to the local processor which can be of importance in a multi-master environment. The priority level can be set by software, thus allowing a muster to dynamically change its priority level to gain control of the bus. The priority of the current Bus Master can be read on the bus, thereby allowing the monitoring of multi-master transactions and facilitating system debugging. Finally, with distributed arbitration there is not problem associated with a detective Bus Master module on the Bus and Interference during replacement is reduced to a minimum. This feature resolves the inherent single point of failure present in all centralized multi-processor architectures.

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6.2.2 TYPE OF MODULES SUPPORTED Three types of boards can be included in a multi-processor G-64 bus system:

1) CPU Masters

CPU boards - can take control of the bus - can send messages and events - can receive messages and events - can receive hardware interrupts

2) Peripheral Masters:

Intelligent I/O boards - can take control of the bus - can generate events - can receive messages - could generate or receive hardware interrupts

3) Slaves:

Memory boards - could generate hardware interrupts I/O boards - cannot take control of the bus (except for DMA operations) - can generate hardware interrupts - cannot generate events

6.2.3 CONFLICT RESOLUTION Each module has a unique identifier of 5-bits. The arbitration mechanism uses this identifier as a priority level in order to resolve contention between several requesters. The priority resolution makes use of the fact that the 6 priority bus lines are driven by open collectors permitting a logical wired-ored combination of all signals driving the same line. (A "low" state always wins over a "high" state).

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When a module wants the bus, it places its unique 5-bit identifier on the P0 P4 (Priority) lines. The sixth line, P5, can be used to demand the bus with the higher priority. This last feature should be used very carefully to ensure a fair access to the bus for all the masters. If another module initiates an arbitration at the same time, the identifiers of the modules get wired-ored on the bus. A priority resolution network, resident on each possible Bus Master module, then examines P0 to P5 lines. If the identifier found on these lines is the same as this of the module, then this module wins the bus. Otherwise, another module with higher priority wins the bus. Fig. 6.1 shows how the priority resolution network is typically implemented. This circuitry performs a real-time comparison between the master input (MP0-MP5) and the number on line P0-P5 on the bus. This comparison is performed using a ripple technique with the most significant priority bits compared first. In case of mismatch, the following stages of the network are disabled, thus removing the module from the arbitration.

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Fig. 6.1 Priority resolution network 83

6.2.4 ARBITRATION UNIT The arbitration scheme of G-64 bus requires that the arbitration logic resides on each Bus Master module. A bus arbitration cycle is totally transparent to the microprocessor on the CPU module. A special circuitry such as the one shown in the block diagram of fig. 6.2 is used between the microprocessor and the Bus. The microprocessor indicates that it wants the bus by merely attempting to access an external memory or peripheral address location. This is done by asserting the VMA, VPA or IACK signals and an external address. The arbitration logic then begins a bus arbitration cycle if it does not already control de bus. After the module has taken control of the bus the data transfer can task place. When the transfer has been completed, the arbitration logic relays the DTACK signal received from the memory/peripheral module to the microprocessor on the processor module. If the processor module is not capable of taking control of the bus because of a higher priority module already controlling it, the arbitration logic will wait indefinitely. It is possible, and recommended, to implement a retry counter that counts how many arbitration cycle has been unsuccessfully attempted. This counter can be connected to a comparator that will temporarily force that arbitration priority to a higher level for the duration of one data transfer. This is achieved by forcing the sixth line, P5 , this last feature should be used very carefully to ensure a fair access to the bus for all the masters. When a processor module has a control of the bus, it must keep it as long as no other processor modules on the bus request it. This feature is named Release On Request (ROR). A processor can keep control of the bus for several data transfer cycles by asserting the internal LOCK signal to the arbitration logic. This causes the arbitration to maintain the bus busy line (BBUSY) active and keep other modules to take control of the bus.

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Fig. 6.2 Arbitration control logic block diagram

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6.2.5 ARBITRATION TIMING Fig. 6.3 shows the timing diagram of the bus arbitration signals on the bus. The flow chart of fig. 6.4 shows the transactions that take place between two master modules in a typical bus arbitration cycle.

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1 Other masters, which complete for control of the bus, must assert their BWD lines 2 BWD low to P0-P5 lines active delay 3 BWD low to BARD low delay 4 If the current master does not need the bus, it must release the BBUSY line (high level) 5 BARD low indicates that arbitration phase is in progress 6 P0-P5 must be stable before the rising edge of BARB 7 The master(s), which have lost the arbitration, must release their BWD lines 8 BBUSY inactive, high level 9 BBUSY low to BWD high delay 10 BWD inactive, high level, before a next arbitration cycle. Note: all values are in [ns] Fig. 6.3 Bus arbitration timing cycle

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Fig. 6.4 Distributed arbitration flow chart 88

6.2.6 DMA IN MULTI-PROCESSOR ENVIRONMENT In a multi-processor environment, bus requesters should incorporate the same arbitration logic as those used in the processor module. In order to maintain compatibility with existing DMA modules, however, the specification allows a scheme that ensures proper functioning of these DMA modules in the new architecture. In addition to insuring compatibility, this scheme allows to maintain system simplicity by using these less sophisticated class of DMA modules. In this scheme, a DMA requester "borrows" the arbitration logic of one Bus Master to take control of bus. This is performing by assigning one of the Bus Masters as the bus arbiter for all DMA requested using the BRQ line. In this case, BRQ is connected to the arbitration logic of one of the up to 31 master modules on the bus and initiate an arbitration cycle on the bus. When the master module wins control of the bus, it asserts the BGRT line instead of the BBUSY to indicate to the DMA requester module that it can take control of the bus. When the DMA module takes the bus, it asserts the BBUSY line, thus keeping all Bus Masters from taking control of the bus. Fig. 6.5 shows the bus timing for a DMA cycle in a multi-processor environment.

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1 Other masters, which complete for control of the bus, must assert their BWD lines. 2 BWD low to P0-P5 lines active delay 3 BWD low to BARB low delay 4 If the current master does not need the bus, it must release the BBUSY line (high level) 5 BARD active low indicates that arbitration phase is in progress 6 P0-P5 must be stable before the rising edge of BARB 7 The master(s), which have lost the arbitration, must release their BWD lines 8 The arbitration logic asserts BGRT line place of BBUSY 9 The DMA requester takes control of the bus by asserting BBUSY low 10 BBUSY low to BRQ high delay 11 BRQ high to BGRT high delay 12 BRQ high to BWD high delay Note: all values are in [ns] Fig. 6.6 Bus timing for a DMA cycle in a multi-processor environment 90

6.3 INTERRUPTS IN MULTI-PROCESSOR ENVIRONMENT There are two kinds of possible interrupts in a G-64 bus multi-processor environment: 1) External Direct Interrupts 2) Events

6.3.1 EXTERNAL DIRECT INTERRUPTS There are six lines on the bus used for direct connection between a CPU Master and one of more interrupt requesters (Peripheral and Slave modules). There are called "hardware" interrupts. An interrupt is signaled by an active level on one of the six interrupt request lines IRQn and NMI. When using external direct interrupts, an interrupt request line must be wired to only one dedicated Bus Master module. This is achieved by enabling /disabling a particular interrupt level on the processor modules. In this way, a Bus Master is dedicated to servicing the interrupts for a particular module or set of modules. This master module will respond to this interrupt in a similar way as in the single-processor mode. A non-vectored (or auto vectored) interrupt will be handled without any access to the bus. In order to respond to a vectored interrupt, the Bus Master module dedicated to interrupt handling must first take control of the bus. An arbitration cycle is automatically initiated by the IACK signal internal to the processor module. After the Bus Master module has taken control of the bus, the IACK signal is propagated to the bus for normal vector acquisition. In the vectored mode, IACK, A0, A1, A2, and the daisy chain are used in the same way as described in chapter 5.6. The NMI line can be directly wired to each master. NMI is a non-vectored interrupt and does not require bus access or arbitration.

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External direct interrupts are the type of interrupts used by all existing G-64 modules. They permit very simple implementation on the peripheral module. These types of interrupts are also the quickest way to service an interrupt. On the other hand, an interrupting module can only interrupt a dedicated processor module and cannot be shared with another Bus Master module.

6.3.2 INTERRUPTS USING EVENTS In a multi-processor system it can be useful to be able to have one interrupting module direct its interrupt to one or more Bus Master modules. Furthermore, it is not possible to maintain an interrupt request asserted as this would lock the bus while the interrupt is being processed. Thus, the interrupt requests are by nature volatile: they are called Events. The Events are subset of the message passing mechanism described in chapter 6.4 of this specification manual. Events is typically a data block of two 16-bit words, containing the ID number of the interrupting module and the ID of the Bus Master module(s) to be interrupted. Events can be generated by peripheral modules.

6.4 MESSAGE PASSING 6.4.1 INTRODUCTION Message passing is a scheme designed to allow very fast hardware inter processor communication. This fast communication is indispensable in order to achieve inter processor communication in a parallel processing architecture. Messages are essentially a data packet that can be sent from any Bus Master module to one or more processors on the bus.

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Events, a special form of the message passing, can be used to replace interrupts when an interrupting device needs to direct the interrupt to a particular processor in the bus.

6.4.2 PRINCIPLE OF OPERATION The message passing is a hardware function of the Bus Master module. To send a message, the processor sets the message passing logic with the message and the destination ID(s). The message passing logic then controls the entire communication process. For message transfer, two different circuits are required: - Sender - Receiver A CPU Master board contains both modules. It can send and receive messages. A Peripheral Master board contains only a sender module because it cannot receive a message. Fig. 6.7 shows the block diagram of a message receiver. During a message passing sequence, all Bus Master modules are listening to the bus to detect and acquire messages. After detecting a message destined to it, the receiver logic will store the data in the receive message buffer. At the end of the transfer, the interrupt logic generates an interrupt to the processor to signal the arrival of a message. The processor must unload the message and store it in its local memory. Then the message will be treated immediately or at a later time according to the processor's decision.

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Fig. 6.6 Message receiver block diagram When a Bus Master wants to send a message it must first store the message in the transmit message buffer. After the buffer has been filled, the processor uses a command to instruct the message passing logic to send. This, in turn, triggers a bus arbitration to win the bus. When the arbitration signals that the bus is available, the message passing logic sends the message previously loaded in the transmit message buffer. Upon completion of the transfer, the interrupt to the processor and releases the bus. Fig. 6.7 shows the block diagram of the message sender logic. 94

Fig. 6.7 Message sender block diagram

95

Fig. 6.8 State diagram of message sender logic

6.4.3 MESSAGE FORMAT A message may be sent to a single CPU Master, a group of CPU Masters, or the whole system (broadcast). The message must, therefore, contain information to define the following parameters: source, destination, type of message and length of the data field. Fig. 6.9 shows a typical message data format.

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Fig. 6.9 Message data format A message is always at least 2 words long. A2-word message is called an "Event" and is principally used as an interrupt in multi-processor architectures. Note that the 3rd and 4th words are only necessary for a group addressing message. 6.4.3.1 DESTINATION ID These 5-bits represent the destination board number. In the G-64 bus, this number is equal to the priority code number of the destination board. The ID number 00000 is not valid identifier and must be ignored by all receivers. 97

6.4.3.2 SOURCE ID These 5-bits represent the source board number. In the G-64 bus, this number is equal to priority code number of the source board. The ID number 00000 is not a valid identifier.

6.4.3.3. CHANNEL ID These 8 bits represent the channel number of the source board. Each number can be assigned to a specific peripheral device which is able to generate an interrupt. This allows 255 different channels on each Bus Master board. The channel number 0 is not valid channel number.

6.4.3.4 LENGTH These 4-bits give the length of the data field in number of words. Maximum length is 16 words. Only data words are included in the count. The values 0, 1-15 represents a range of 16, 1-15 respectively.

6.4.3.5 TYPE These 4-bits are reserved to specify the type of message. The following types are defined in the specification. type Message type 0001 0010 0100 1000

Point to point message Group addressing message Broadcast message Event message

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6.4.3.5 GROUP ADDRESS This 2-word field is active only for group addressing type of messages. Each bit position (0-31) is assigned to one of the 31 possible Bus Master modules ID. The first word contains bits 0 to 15. The second word contains bits 16 to 31. A bit set indicates that the associated Bus Master is addressed. Bit 0 is not assigned to any Bus Master module. 6.4.3.6 DATA FIELD The data field contains up to 16 words of data. No restrictions are made on the type of information in this field.

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6.4.4 MESSAGE PASSING TIMING A message transfer is characterized by VED (Valid Event Data) signal low. VED remains low for the entire duration of the message transfer. Each data word is validated by DS0 and DS1 (Data Strobe) low. After the falling edge of VED, the DTACK signal of all receiver modules must be pulled to a low level. The message receiver modules(s) acknowledge each data word by releasing their DTACK signal. When VED is asserted, VMA and VPA are negated and R/W is in the write mode. The end of a message passing sequence is indicated by the release of the VED signal shortly before the release of the DS0 and DS1 signals. A message passing transfer and timing illustrated in fig. 6.10.

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1 VED low DS0, DS1 active low delay 2 All message receiver modules must set their DTACK low during this delay 3 Data se-up time 4 When DTACK is high, all message receiver modules have accepted the data 5 Data hold time 6 Assertion of DS0, DS1 indicates that a new word data available 7-8 Same as 2-3 9 DTACK high to VED released (high level) 10 VED high to DS0, DS1 high delay on the last word of transfer 11 Data hold time 12 In case of error BERR signal can be asserted at any moment of a data transfer 13 DS0, DS1 high to BERR released (high level) delay Note: all value are in [ns]

Fig. 6.11 Message passing timing diagram 101

6.4.5 EXCEPTION HANDLING In a message passing cycle, a receiver can generate a bus error BERR to indicate that it cannot accept the message. This can occur if the receive message buffer(s) has not been emptied by its processor. BERR is used by the message passing transmit logic to abort the transmission sequence if one or more receivers failed to acknowledge the transfer within a predefined time.

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TABLE OF CONTENTS FOREWORD

3

CHAPTER 1. GENERAL INFORMATION

5

1.1 INTRODUCTION 1.2 TYPE OF MODULES SUPPORTED 1.3 FEATURES 1.4 SPECIFICATIONS

5 7 8 9

CHAPTER 2. MECHANICAL SPECIFICATIONS

11

2.1 INTRODUCTION 2.2 G-64 CONNECORS 2.3 G-64 MODULES 2.4 BACKPLANE

11 11 12 13

CHAPTER 3. ELECTRICAL SPECIFICATIONS

17

3.1 INTRODUCTION 3.2 POWER SUPPLY 3.3. BACKPLANES 3.3.1 BACKPLANE WITHOUT TERMINATORS 3.3.2 BACKPLANE WITH TERMINATORS 3.3.3 BACKPLANE SPECIFICATIONS 3.4 BUS TERMINATORS 3.5 G-64 BUS CONNECTOR 3.6 DRIVER CHARACTERISTICS 3.7 RECEIVER CHARACTERISTICS 3.8 TRANSCEIVER CHARACTERISTICS 3.9 SIGNAL ELECTRICAL CHARACTERISTICS

17 17 18 18 18 19 20 21 22 23 23 24

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CHAPTER 4. BUS SIGNAL DESCRIPTION 4.1 INTRODUCTION 4.2 D0 D15 4.3.1 A0-A15 4.3.2 A0-A23 4.3.2 A0-A23: D16-D31 4.4 Page 4.5 DS0, DS1 4.6 VMA 4.7 VPA 4.8 BRQ 4.9 BGRT 4.10 BBUSY 4.11 IRQ5, IRQ3 4.12 IRQ1, IRQ2, IRQ4 4.13 NMI 4.14 PWF 4.15 IACK 4.16 CHIN, CHOUT 4.17 BERR 4.18 ENABLE 4.19 SYCLK 4.20 R/W 4.21 RDY or DTACK 4.22 HALT 4.23 RESET 4.24 SYSFAIL 4.25 P0 - P5 4.26 VED 4.27 BWD 4.28 BARB 4.29 LWORD

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25 25 25 26 26 26 27 27 28 28 29 29 30 30 30 31 31 31 32 33 33 34 34 35 36 36 36 37 37 38 38 39

CHAPTER 5. DYNAMIC OPERATION

41

5.1 INTRODUCTION 5.2 SYMBOLS USED IN TIMING DIAGRAM 5.3 SYNCHRONOUS OPERATION 5.3.1 INTRODUCTION 5.3.2 READ-WRITE OPERATION 5.3.3 MEMORY AND I/O READ/WRITE CYCLE 5.3.5 SLOW DEVICE CYCLE 5.4. 16-BIT ASYNCHRONOUS OPERATION 5.4.1 INTRODUCTION 5.4.2 16-BIT BUS ALIGNMENT 5.4.3 READ-WRITE OPERATION 5.4.3 MEMORY AND I/O WRITE CYCLE 5.4.4 MEMORY AND I/O READ CYCLE 5.4.5 READ-MODIFY-WRITE CYCLE (RMW) 5.5. 32-BIT ASYNCHRONOUS OPERATION 5.5.1 INTRODUCTION 5.5.2 32-BIT BUS ALIGNMENT 5.5.3 32-BIT MEMORY WRITE CYCLE 5.5.4 32-BIT MEMORY READ CYCLE 5.5.5 32-BIT READ-MODIFY-WRITE CYCLE (RMW) 5.6 LOCKED TRANSFER CYCLES 5.7 INTERRUPTS 5.7.1 INTRODUCTION 5.7.2 AUTO-VECTORED INTERRUPTS 5.7.3 VECTORED INTERRUPTS 5.7.4 SYNCHRONOUS INTERRUPTS VECTOR READ CYCLE 5.7.5 ASYNCHRONOUS INTERRUPT VECTOR READ CYCLE 5.7.6 NON MASKABLE INTERRUPT 5.7.7 POWER FAIL 5.8 BUS ERROR 5.9 BUS SHARE

41 41 42 42 42 42 44 46 46 46 47 48 50 52 54 54 54 56 58 60 62 63 63 63 63

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64 65 67 68 69 70

5.10 DAISY CHAIN 5.10.1 GENERAL INFORMATION 5.10.2 DAISY CHAIN CIRCUIT FOR INTERRUPTS 5.10.3 DAISY CHAIN CIRCUIT FOR BUS REQUESTS 5.10.4 DAISY CHAIN TIMING 5.11 SYSTEM RESET 5.12 SYSTEM CLOCK

71 71 72 74 75 76 77

CHAPTER 6. MULTI-PROCESSOR MODE

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6.1 INTRODUCTION 6.2 ARBITRATION 6.2.1 ARBITRATION DESCRIPTION 6.2.2 TYPE OF MODULES SUPPORTED 6.2.3 CONFLICT RESOLUTION 6.2.4 ARBITRATION UNIT 6.2.5 ARBITRATION TIMING 6.2.6 DMA IN MULTI-PROCESSOR ENVIRONMENT 6.3 INTERRUPTS IN MULTI-PROCESSOR ENVIRONMENT 6.3.1 EXTERNAL DIRECT INTERRUPTS 6.3.2 INTERRUPTS USING EVENTS 6.4 MESSAGE PASSING 6.4.1 INTRODUCTION 6.4.2 PRINCIPLE OF OPERATION 6.4.3 MESSAGE FORMAT 6.4.3.1 DESTINATION ID 6.4.3.2 SOURCE ID 6.4.3.3 CHANNEL ID 6.4.3.4 LENGTH 6.4.3.5 TYPE 6.4.3.5 GROUP ADDRESS 6.4.3.6 DATA FIELD 6.4.4 MESSAGE PASSING TIMING 6.4.5 EXCEPTION HANDLING

79 80 80 81 81 84 87 89

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91 91 92 92 92 93 96 97 98 98 98 98 99 99 100 102

TABLE OF FIGURES Fig. 2.1a Module connector for G-64 standard Fig. 2.1b backplane connector for G-64 standard Fig. 2.2 G-64 module mechanical characteristics Fig. 2.3 G-64 backplane mechanical characteristics Fig. 3.1 Multi-layer backplane structure Fig. 3.2 64 bus termination Fig. 3.3 Signal levels Fig. 5.1 Signal symbols Fig. 5.2 Memory and I/O synchronous read/write cycles Fig. 5.3 Slow cycle - synchronous mode Fig. 5.4 16-bit bus alignment scheme Fig. 5.5 Asynchronous write cycle Fig. 5.6 Asynchronous read cycle Fig. 5.7 Asynchronous read-modify-write cycle Fig. 5.8 32-bit bus alignment scheme Fig. 5.9 Asynchronous write cycle Fig. 5.10 Asynchronous read cycle Fig. 5.11 Asynchronous read-modify-write cycle Fig. 5.12 Locked transfer cycles Fig. 5.13 IACK synchronous cycle Fig. 5.14 IACK asynchronous cycle Fig. 5.15 Single cycle NMI - synchronous mode Fig. 5.16 Single cycle NMI - asynchronous mode Fig. 5.17 Power fail interrupt timing Fig. 5.18 BERR timing Fig. 5.19 DMA bus request timing - asynchronous mode Fig. 5.20 Module arrangement for use of daisy chain Fig. 5.21 daisy chain circuitry for interrupts Fig. 5.22 practical implementation using GESPAC interrupt handler IC Fig. 5.23 Daisy chain circuitry for bus requesters (DMA) Fig. 5.24 Daisy chain timing example Fig. 5.25 Power up/down reset Fig. 5.26 SYCLK - system clock timing Fig. 6.1 Priority resolution network 107

11 12 14 15 19 21 24 41 43 45 47 48 50 52 55 56 58 60 62 64 66 67 67 68 69 70 71 72 73 74 75 76 77 83

Fig. 6.2 Arbitration control logic block diagram Fig. 6.3 GS81MPA_Multi-processor Arbitrator IC pinout Fig. 6.4 Bus arbitration timing cycle Fig. 6.5 Distributed arbitration flow chart Fig. 6.6 Bus timing for a DMA cycle in a multi-processor environment Fig. 6.7 Message receiver block diagram Fig. 6.8 Message sender block diagram Fig. 6.9 State diagram of message sender logic Fig. 6.10 Message data format Fig. 6.11 Message passing timing diagram

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85 86 87 88 90 94 95 97 97 101