... pattern to the wafer surface. â Process the wafer to physically pattern each layer of the IC ... (photo resist: light-sensitive organic polymer). ⢠The photoresist is exposed to ultra violet light: ... active by an rf-generated plasma anisotropic etch ...
Introduction Transistors The CMOS inverter Technology
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Scaling Gates Sequential circuits Storage elements Phase-Locked Loops Example
– – – – –
Lithography Physical structure CMOS fabrication sequence Advanced CMOS process Process enhancements
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CMOS technology •
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An Integrated Circuit is an electronic network fabricated in a single piece of a semiconductor material The semiconductor surface is subjected to various processing steps in which impurities and other materials are added with specific geometrical patterns The fabrication steps are sequenced to form three dimensional regions that act as transistors and interconnects that form the switching or amplification network
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Lithography Lithography: process used to transfer patterns to each layer of the IC Lithography sequence steps: • Designer:
– Drawing the “layer” patterns on a layout editor
• Silicon Foundry: – Masks generation from the layer patterns in the design data base – Printing: transfer the mask pattern to the wafer surface – Process the wafer to physically pattern each layer of the IC
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Lithography Basic sequence •
1. Photoresist coating
The surface to be patterned is: – spin-coated with photoresist – the photoresist is dehydrated in an oven (photo resist: light-sensitive organic polymer)
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The photoresist is exposed to ultra violet light: – For a positive photoresist exposed areas become soluble and non exposed areas remain hard
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The soluble photoresist is chemically removed (development). – The patterned photoresist will now serve as an etching mask for the SiO2
Photoresist
SiO2 Substrate 2. Exposure Opaque
Ultra violet light
Mask Exposed
Unexposed
Substrate 3. Development
Substrate
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Lithography •
The SiO2 is etched away leaving the substrate exposed:
4. Etching
– the patterned resist is used as the etching mask
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Ion Implantation:
Substrate
– the substrate is subjected to highly energized donor or acceptor atoms – The atoms impinge on the surface and travel below it – The patterned silicon SiO2 serves as an implantation mask
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The doping is further driven into the bulk by a thermal cycle
5. Ion implant
Substrate 6. After doping
diffusion
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Lithography • The lithographic sequence is repeated for each physical layer used to construct the IC. The sequence is always the same: – – – –
Photoresist application Printing (exposure) Development Etching
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Lithography Patterning a layer above the silicon surface 1. Polysilicon deposition
4. Photoresist development
Polysilicon
SiO2 Substrate 2. Photoresist coating
Substrate 5. Polysilicon etching
photoresist
Substrate 3. Exposure
Substrate
UV light 6. Final polysilicon pattern
Substrate Paulo Moreira
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Lithography •
Etching: – – – –
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anisotropic etch (ideal)
Process of removing unprotected material Etching occurs in all directions Horizontal etching causes an under cut “preferential” etching can be used to minimize the undercut
Etching techniques: – –
Wet etching: uses chemicals to remove the unprotected materials Dry or plasma etching: uses ionized gases rendered chemically active by an rf-generated plasma
CMOS power budget: â Dynamic power consumption: ⢠Charging and discharging of capacitors. â Short circuit currents: ⢠Short circuit path between power rails ...
The CMOS inverter. ⢠Technology. ⢠Scaling. ⢠Gates ..... For acceptable phase margin. Place the zero 1/Ï .... Add VCO phase noise. Update the VCO period ...
D. A. Johns and K. Martin, âAnalog Integrated Circuit Design,â John Wiley & Sons 1997, ISBN 0- ... B. Razavi, âA Study of Phase Noise in CMOS Oscillators,â IEEE Journal on Solid-State ... http://www.ife.ee.ethz.ch/~ichsc/ichsc_chapter11.pdf.
Dec 17, 2004 - M.J.M. Pelgrom et al., âA 25-Ms/s 8-bit CMOS A/D Converter for Embedded Applicationâ, ... components can be attributed to two classes of effects. .... Technical Digest of the IEEE International Electron Device Meeting 1997, pp ...
Design of Analog Integrated Circuits and Systems by Kenneth R. ... Design of Analog CMOS Integrated Circuits ... CMOS Circuit Design, Layout, and Simulation.
Clock skew control and frequency multiplication. Ext. CLK. Clock pad. PLL ...... Algorithm: ⢠Slice the time in very thin intervals (much smaller than T vco. ).
The silicon area of large memory cells is dominated by the size of the memory core, it is thus crucial to keep the size of the basic storage cell as small as possible.
An active low pass filter. ⢠A charge-pump and a capacitor .... Can we run the starved inverter infinitely slow?. ⢠... Signal and the Inverted signal available.
that of a DLL you notice some similarities but as well some very fundamental differences: .... 3rd always buffer the VCO signal to make the transfer ..... âMonolithic Phase-Locked Loops and Clock Recovery Circuits Theory and Design,â ..... In one
in the vernier scale (lower) lines up with a tick mark in the reference scale (upper). [36]. 38 ..... Almasi, L. et al., New TDC electronics for a PesTOF tower â in NA49, ... Mota, M., A high-resolution Time-to-Digital Converter â users manual, C
NRZI non-return to zero invert on ones. â Manchester and Bi-Phase Mark. â 3B/4B, 5B/6B and 8B/10B, done in groups of bits before serialization. BiPhase Mark.
... CMS tracker analogue data link. â The CMS tracker data path. â The linear laser-driver ... Monitoring. Serial/Parallel. Local. Address. Control & Data. Interface.
Tx. Detector channel. LHC clock (40MHz). Gain. 82 728 chan n e ls (barrel +. 2 en d caps). Radiation hard environment. CMS Electromagnetic Calorimeter.
May 20, 2007 - Below an excerpt form correspondence with Hans Camenzind: ..... This means that any spectral content of the phase noise that is above 10 ...
Dec 17, 2004 - The definition of âMoore's Lawâ has come to refer to almost anything related to ..... The following data are taken from the design manuals of different CMOS technologies. N. D. Arora et al., "Modeling the Polysilicon Depletion Effe
Sep 29, 2005 - Diameter controlled by seed catalyst. ⢠Can be microns long. ⢠Control electrical properties via doping. â Materials in environment during growth.
