data sheet

Nov 11, 2003 - The vision IF and mono intercarrier sound circuit can be used for the .... outlined in the SRS Trademark Usage Manual separately provided. Philips ...... STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP ...... when a page is acquired off air i.e.: rolling headers and time are not ...
1MB taille 25 téléchargements 484 vues
INTEGRATED CIRCUITS

DEVICE DATASPECIFICATION SHEET

UOCIII series Versatile signal processor for lowand mid-range TV applications Preliminary specification File under18Integrated Circuits, Version:

2003 Nov 11 Previous date: 2003 Oct 09

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

GENERAL DESCRIPTION The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH embedded TEXT/Control/Graphics µ-Controller (TCG µ-Controller) and US Closed Caption decoder. In addition the following functions can be added: • Adaptive digital (4H/2H) PAL/NTSC combfilter • Teletext decoder with 10 page text memory • Multi-standard stereo decoder

FEATURES

• BTSC stereo decoder

Analogue Video Processing (all versions)

• Digital sound processing circuit

• Multi-standard vision IF circuit with alignment-free PLL demodulator

• Digital video processing circuit

• Internal (switchable) time-constant for the IF-AGC circuit

The UOCIII series consists of the following 3 basic concepts:

• Switchable group delay correction and sound trap (with switchable centre frequency) for the demodulated CVBS signal

• Stereo versions. These versions contain the TV processor with a stereo audio selector, the TCG µ-Controller, the multi-standard stereo or BTSC decoder, the digital sound processing circuit and the digital video processing circuit. Options are the adaptive digital PAL/NTSC comb filter and a teletext decoder with 10 page text memory.

• DVB/VSB IF circuit for preprocessing of digital TV signals. • Video switch with 3 external CVBS inputs and a CVBS output. All CVBS inputs can be used as Y-input for Y/C signals. However, only 2 Y/C sources can be selected because the circuit has 2 chroma inputs. It is possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the YUV interface and the RGB/YPRPB input are not needed.

• AV stereo versions. These versions contain the TV processor with stereo audio selector and the TCG µ-Controller. Options are the digital sound processing circuit, the digital video processing circuit, the adaptive digital PAL/NTSC comb filter and a teletext decoder with a 10 page text memory.

• Automatic Y/C signal detector • Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the chrominance signal.

• Mono sound versions. These versions contain the TV processor with a selector for mono audio signals and the TCG µ-Controller. Options are the adaptive digital PAL/NTSC combfilter and a teletext decoder with 10 page text memory.

• Integrated luminance delay line with adjustable delay time • Picture improvement features with peaking (with switchable centre frequency, depeaking, variable positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic skin tone control, gamma control and blue- and black stretching. All features are available for CVBS, Y/C and RGB/YPBPR signals.

The most important features of the complete IC series are given in the following feature lists. The exact feature content of the various ICs is given in Table 1 on page 7. The ICs are mounted in a QFP-128 envelope(1) and can be used in economy television receivers with 90° and 110° picture tubes. They have supply voltages of 5V, 3.3V. Also an 1.8V supply is needed, but this can be simply derived by adding an emitter follower at a reference voltage from the device.

• Switchable DC transfer ratio for the luminance signal • Only one reference (24.576 MHz) crystal required for the TCG µ-Controller, digital sound processor, Teletextand the colour decoder

UOCIII is supported by a comprehensive Global TV Software Development kit to enable easy programming and fast time-to-market (see also Chapter “LICENSE INFORMATION” on page 6.

• Multi-standard colour decoder with automatic search system and various “forced mode” possibilities • Internal base-band delay line

(1) Both standard and “face down” versions of the QFP128 0.8mm pitch package are available.

2003 Nov 11

2

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications • Indication of the Signal-to-Noise ratio of the incoming CVBS signal

UOCIII series Sound Demodulation (all versions) • Separate SIF (Sound IF) input for single reference QSS (Quasi Split Sound) demodulation.

• Linear RGB/YPBPR input with fast insertion. • YUV interface. When this feature is not required some pins can be used as additional RGB/YPBPR input. It is also possible to use these pins for additional CVBS (or Y/C) input (CVBS/YX and CX).

• AM demodulator without extra reference circuit • The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this demodulator is optional for special applications. Normally the FM demodulators of the stereo demodulator/decoder part are used (see below).

• Tint control for external RGB/YPBPR signals • Scan Velocity Modulation output. The SVM circuit is active for all the incoming CVBS, Y/C and RGB/YPBPR signals. The SVM function can also be used during the display of teletext pages. • RGB control circuit with ‘Continuous Cathode Calibration’, white point and black level off-set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently.

• The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second sound channel can be demodulated. In such an application it is necessary that an external bandpass filter is inserted. • The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be demodulated.

• Contrast reduction possibility during mixed-mode of OSD and Text signals • Adjustable ‘wide blanking’ of the RGB outputs • Horizontal synchronization with two control loops and alignment-free horizontal oscillator

• Switch to select between 2nd SIF from QSS demodulation or external FM (SSIF)

• Vertical count-down circuit • Vertical driver optimized for DC-coupled vertical output stages

Audio Interfaces and switching (stereo versions with Audio DSP)

• Horizontal and vertical geometry processing with horizontal parallelogram and bow correction and horizontal and vertical zoom

• Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for HEADPHONE. The headphone channel has an analogue volume control circuit for the L and R channel. Finally 1 stereo SPEAKER output with digital controls.

• Low-power start-up of the horizontal drive circuit

• AVL (Automatic Volume Levelling) circuit for the headphone channel.

Analogue video processing (stereo versions) • The low-pass filtered ‘mixed down’ I signal is available via a single ended or balanced output stage.

• Digital input crossbar switch for all digital signal sources and destinations

Analogue video processing (mono versions)

• Digital output crossbar for exchange of channel processing functionality

• The low-pass filtered ‘mixed down’ I signal is available via a single ended output stage

• Digital audio input interface (stereo I2S input interface) • Digital audio output interface (stereo I2S output interface)

Digital Video Processing (some versions) • Double Window mode applications. It is possible to display a video and a text window or 2 text windows in parallel.

Audio interfaces and switching (AV stereo versions without Audio DSP)

• Linear and non-linear horizontal scaling of the video signal to be displayed.

• Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH and a stereo SPEAKER output with analogue volume control. • Analogue mono AVL circuit at left audio channel

2003 Nov 11

3

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series Volume and tone control for loudspeakers (stereo versions with Audio DSP)

Audio interfaces and switching (mono versions) • Audio switch circuit with 4 external audio (mono) inputs and a volume controlled output

• Automatic Volume Level (AVL) control • Smooth volume control

• AVL circuit

• Master volume control

Stereo Demodulator and Decoder (full stereo versions)

• Soft-mute • Loudness

• Demodulator and Decoder Easy Programming (DDEP)

• Bass, Treble

• Auto standard detection (ASD)

• Dynamic Bass Boost (DBB) (2)

• Static Standard Selection (SSS)

• Dynamic Virtual Bass (DVB) (3)

• DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation

• BBE® Sound processing (4)

• NICAM decoding (B/G, I, D/K and L standard)

• Graphic equaliser

• Two-carrier multistandard FM demodulation (B/G, D/K and M standard)

• Programmable beeper

• Processed or non processed subwoofer

• Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound

Reflection and delay for loudspeaker channels (stereo versions with Audio DSP)

• Adaptive de-emphasis for satellite FM

• Dolby® Pro Logic® Delay (1)

• Optional AM demodulation for system L, simultaneously with NICAM

• Pseudo hall/matrix function

• Identification A2 systems (B/G, D/K and M standard) with different identification time constants

Psycho acoustic spatial algorithms, downmix and split in loudspeaker channels (stereo versions with Audio DSP)

• FM pilot carrier present detector • Monitor selection for FM/AM DC values and signals, with peak and quasi peak detection option

• Extended Pseudo Stereo (EPS) (5) • Extended Spatial Stereo (ESS) (6)

• BTSC MPX decoder

• Virtual Dolby® Surround (VDS 422,423) (1)

• SAP decoder

• SRS 3D and SRS TruSurround® (4)

• dbx® noise reduction (4) • Japan (EIAJ) decoder

RDS/RBDS

• FM radio decoder

• Demodulation of the European Radio Data system (RDS) or the USA Radio Broadcast Data System (RBDS) signal

• Soft-mute for DEMDEC outputs DEC, MONO and SAP • FM overmodulation adaptation option to avoid clipping and distortion

• RDS and RBDS block detection • Error detection and correction

Audio Multi Channel Decoder (stereo versions with Audio DSP)

• Fast block synchronisation • Synchronisation control (flywheel)

• Dolby® Pro Logic® (DPL) (1)

• Mode control for RDS/RBDS processing

• Five channel processing for Main Left and Right, Subwoofer, Centre and Surround. To exploit this feature an external DAC is required.

• Different RDS/RBDS block information output modes (2) Also referred to as “Dynamic UltraBass” (3) Also referred to as “Dynamic Bass Enhancement” (4) For the use of these products a licence is required. More details are given in the chapter “LICENSE INFORMATION” on page 6 (5) Also referred to as “I-Mono” or “Incredible Mono” (6) Also referred to as “I-Stereo” or “Incredible Stereo”

(1) Dolby is a trademark of Dolby Laboratories

2003 Nov 11

4

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

µ-Controller

Display

• 80C51 µ-controller core standard instruction set and timing

• Teletext and Enhanced OSD modes

• 0.4883 µs machine cycle

• 50Hz/60Hz display timing modes

• Features of level 1.5 WST and US Close Caption

• maximum of 256k x 8-bit flash programmable ROM

• Two page operation for 16:9 screens

• maximum of 8k x 8-bit Auxiliary RAM

• Serial and Parallel Display Attributes

• 12-level Interrupt controller for individual enable/disable with two level priority

• Single/Double/Quadruple Width and Height for characters

• Two 16-bit Timer/Counter registers • One 24-bit Timer (16-bit timer with 8-bit Pre-scaler)

• Smoothing capability of both Double Size, Double Width & Double Height characters

• WatchDog timer

• Scrolling of display region

• Auxiliary RAM page pointer

• Variable flash rate controlled by software

• 16-bit Data pointer

• Soft colours using CLUT with 4096 colour palette

• Stand-by, Idle and Power Down modes

• Globally selectable scan lines per row (9/10/13/16/) and character matrix [12x9, 12x13, 12x16, 16x18, (VxH)]

• 24 general-purpose I/O pins

• Fringing (Shadow) selectable from N-S-E-W direction

• 14 bits PWM for Voltage Synthesis Tuning

• Fringe colour selectable

• 8-bit A/D converter with 4 multiplexed inputs

• Contrast reduction of defined area

• 5 PWM (6-bits) outputs for analogue control functions

• Cursor

• Remote Control Pre-processor (RCP) • Universal Asynchronous Receiver Transmitter (UART)

• Special Graphics Characters with two planes, allowing four colours per character

Data Capture

• 64 software redefinable On-Screen display characters

• Text memory up to 10 pages

• 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic)

• Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT)

• G1 Mosaic graphics, Limited G3 Line drawing characters • WST Character sets and Closed Caption Character set in single device

• Data Capture for US Closed Caption • Data Capture for 525/625 line WST, VPS (PDC system A) and 625 line Wide Screen Signalling (WSS) bit decoding

• SVM for Text

• Automatic selection between 525 WST/625 WST • Automatic selection between 625 WST/VPS on line 16 of VBI • Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput • Automatic detection of FASTEXT transmission • Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters • Signal quality detector for video and WST/VPS data types • Comprehensive teletext language coverage • Vertical Blanking Interval (VBI) data capture of WST data

2003 Nov 11

5

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

LICENSE INFORMATION dbx dbx is a registered trademark of Carillon Electronics Corp. A license is required for the use of this product. For further information, please contact THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA. Tel: 1-508-478-9200, FAX: 1-508-478-0990 Dolby “Dolby”, “Pro Logic” and the double-D symbol are trademarks of Dolby Laboratories, San Francisco, USA, products are available to licensees of Dolby Laboratories Licensing Corporation, 100 Potrero Avenue, San Francisco, CA, 94103, USA, Tel: 1-415-558-0200, Fax: 1-415-863-1373 Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. BBE BBE is a registered trademark of BBE Sound, Inc., 5381 Production Drive, Huntington Beach, California 92649, USA. The use of BBE needs licensing from BBE Sound, Inc. Tel: 1-714-897-6766, Fax: 1-714-895-6728

The SRS TruSurround technology rights incorporated in the TDA120xxH are owned by SRS Labs, a U.S. Corporation and licensed to Philips Semiconductors B.V. Purchaser of TDA120xxH must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the TDA120xxH must be sent to SRS Labs for review. SRS and TruSurround are protected under US and foreign patents issued and/or pending. TruSurround, SRS and (O) symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the chip TDA120xxH, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. Philips “Dynamic Ultra BassTM”, “Dynamic Bass Enhancement”, “I-Mono” and “I-Stereo” are denominators for Philips patented technologies. The use of the IC does not imply any copyrights nor the right to use the same denominators but instead generic ones such as listed below. Generic name/ Philips name • Dynamic Virtual Bass (DVB)/Dynamic UltraBass • Dynamic Bass Boost (DBB)/Dynamic Bass Enhancement • Extended Pseudo Stereo (EPS)/I-Mono • Extended Spatial Stereo (ESSI)/I-Stereo GTV Delivery and use of the GTV Software Development Kit requires a separate License sold by Philips Semiconductors B.V. Please contact your nearest Philips Semiconductors sales office for further details. 2003 Nov 11

6

CONFIDENTIAL

NTSC



128

4

1.25 2.25



NTSC



128

4

1.25 2.25

MULTI



128

4

1.25 2.25



MULTI



128

4

1.25 2.25

MULTI



128

4





√ √

TDA12001H/H1(2) BTSC(3)





TDA12006H/H1

BTSC(3)





TDA12007H/H1

BTSC(3)





TDA12008H/H1

BTSC(3)





TDA12009H/H1

BTSC(3)





TDA12010H/H1(2)

MULTI





TDA12011H/H1(2)

MULTI





TDA12016H/H1

MULTI





TDA12017H/H1

MULTI





TDA12018H/H1

MULTI





TDA12019H/H1

MULTI





TDA12020H/H1(2)

MULTI





TDA12021H/H1(2)

MULTI





TDA12026H/H1

MULTI





TDA12027H/H1

MULTI





TDA12028H/H1

MULTI





TDA12029H/H1

MULTI





√ √ √ √ √ √ √ √ √ √



MULTI

2.25

10

2.25

128

4

NTSC





128/256

8

1.25 2.25

NTSC





128/256

8

1.25 2.25

NTSC











128/256

8

1.25 2.25

NTSC











128/256

8

1.25 2.25

NTSC



















128/256

8

1.25 2.25















NTSC





128/256

8

1.25 2.25

MULTI





128/256

8

1.25 2.25

MULTI





128/256

8

1.25 2.25

MULTI











128/256

8

1.25 2.25

MULTI











128/256

8

1.25 2.25

MULTI



















128/256

8

1.25 2.25

MULTI



















128/256

8

1.25 2.25

MULTI





128/256

8

10

2.25

MULTI





128/256

8

10

2.25

MULTI







128/256

8

10

2.25

MULTI









128/256

8

10

2.25

MULTI



















128/256

8

10

2.25

MULTI



















128/256

8

10

2.25







Preliminary specification



10

UOCIII series

TDA12000H/H1(2) BTSC(3)

DRCS RAM (k)



DISPLAY RAM (k)

TDA11020H/H1

AUX RAM SIZE (k)

√ √

ROM SIZE (k)

√ √

TDA11021H/H1

7

CONFIDENTIAL

TDA11010H/H1 TDA11011H/H1

DW / PANORAMA



BBETM



SRS® TruSurround

TDA11001H/H1

SRS® 3D Stereo



Virtual Dolby® (VDS)



Dolby® ProLogic®

TDA11000H/H1

10

dbx®

0

RDS/RBDS

STEREO AUDIO DECOMONO DSP DER

MONO FM RADIO

TYPE NUMBER(1)

STEREO FM RADIO

NUMBER OF TELETEXT PAGES

COLOUR DECODER

SOUND SYSTEM

Philips Semiconductors

Overview of types

Versatile signal processor for low- and mid-range TV applications

Table 1

COMB FILTER

2003 Nov 11

OVERVIEW OF THE VARIOUS VERSIONS







√ √

TDA12071H/H1



TDA12072H/H1(2)



TDA12073H/H1(2)



TDA12076H/H1





TDA12077H/H1





TDA12078H/H1





TDA12079H/H1





√ √ √ √



128/256

8

1.25 2.25

MULTI



128/256

8

1.25 2.25

MULTI



128/256

8

1.25 2.25

MULTI



128/256

8

1.25 2.25

MULTI











128/256

8

1.25 2.25

MULTI











128/256

8

1.25 2.25

MULTI

















128/256

8

1.25 2.25

MULTI

















128/256

8

1.25 2.25

MULTI



128/256

8

10

2.25

MULTI



128/256

8

10

2.25

MULTI



128/256

8

10

2.25

MULTI



128/256

8

10

2.25

MULTI











128/256

8

10

2.25

MULTI











128/256

8

10

2.25

MULTI

















128/256

8

10

2.25

MULTI

















128/256

8

10

2.25

Philips Semiconductors



TDA12069H/H1

MULTI

Versatile signal processor for low- and mid-range TV applications

TDA12068H/H1



DRCS RAM (k)



DISPLAY RAM (k)



AUX RAM SIZE (k)

TDA12067H/H1



ROM SIZE (k)



DW / PANORAMA



TDA12070H/H1 8

CONFIDENTIAL

TDA12066H/H1

BBETM



TDA12063H/H1(2)

SRS® TruSurround





SRS® 3D Stereo



TDA12062H/H1(2)

Virtual Dolby® (VDS)

TDA12061H/H1

Dolby® ProLogic®



dbx®

TDA12060H/H1

10

RDS/RBDS

0

MONO FM RADIO

STEREO AUDIO DECOMONO DSP DER

STEREO FM RADIO

TYPE NUMBER(1)

COLOUR DECODER

NUMBER OF TELETEXT PAGES

COMB FILTER

2003 Nov 11

SOUND SYSTEM

Note 1. The “standard” version is indicated with “H” and the “facedown” version with “H1” 2. For these versions the feature content can be found from the type number. More details are given in the next Section. 3. When the BTSC demodulation is active the EIAJ demodulation is also activated. Preliminary specification

UOCIII series

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

Type Number Definition and Feature Indication The complete type number of these versions is given below.

TDA12000H1/N1VXY0AA The explanation of the various parts of the type number is given below: • The first 8 characters indicate the type number, the last 2 characters vary depending on the version. • The next 1 or 2 characters indicate the envelope. The normal QFP128 version is indicated with “H” and the “face-down version” with “H1”. • The first 3 characters after the slash (/) indicate the IC version. • The characters “X” and “Y” give an indication of the Feature Content. More information is given in the Tables 2 and 3. • The last 3 characters give an indication of the ROM code.

Dolby® ProLogic®

Virtual Dolby® (VDS)

0

0

0

0

0

SECOND INDICATION (Y)

SRS® 3D Stereo

SRS® TruSurround

BBETM

DW / PANORAMA

Feature Indication, second character (Y)

dbx®

Table 3

ROM size / 0 = 128K

Feature Indication, first character (X)

FIRST INDICATION (X)

Table 2

1

0

0

0

1

0

0

0

0

0

0

0

0

1

2

0

0

1

0

1

3

0

0

1

1

2

0

0

1

0

4

0

1

0

0

3

0

0

1

1

0

1

0

0

5

0

1

0

1

4

6

0

1

1

0

5

0

1

0

1

7

0

1

1

1

6

0

1

1

0

0

1

1

1

8

1

0

0

0

7

9

1

0

0

1

8

1

0

0

0

A

1

0

1

0

9

1

0

0

1

1

0

1

0

B

1

0

1

1

A

C

1

1

0

0

B

1

0

1

1

D

1

1

0

1

C

1

1

0

0

1

1

0

1

E

1

1

1

0

D

F

1

1

1

1

E

1

1

1

0

F

1

1

1

1

2003 Nov 11

9

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

QUICK REFERENCE DATA SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Supply VP

analogue supply voltage TV processor

4.7

5.0

5.3

V

IP

supply current (5.0 V)



190



mA

VDDA

digital supply TV processor / analogue supply periphery

3.0

3.3

3.6

V

IDDA

supply current (3.3 V)



36



mA

VDDC/P

digital supply to core/periphery

1.65

1.8

1.95

V

IDDC/P

supply current (1.8 V)



440



mA

VPAudio (1)

audio supply voltage

4.7

8.0

8.4

V

supply current (5.0/8.0 V)



0.5



mA

total power dissipation



1.87



W

ViVIFrms)

video IF amplifier sensitivity (RMS value)



75

150

µV

ViSIF(rms)

QSS sound IF amplifier sensitivity (RMS value)



45

tbf

dBµV

ViSSIF(rms)

sound IF amplifier sensitivity (RMS value)



1.0



mV

ViAUDIO(rms)

external audio input (RMS value)



1.0

1.3

V

ViCVBS(p-p)

external CVBS/Y input (peak-to-peak value)



1.0

1.4

V

ViCHROMA(p-p)

external chroma input voltage (burst amplitude) (peak-to-peak value)



0.3

1.0

V

ViRGB(p-p)

RGB inputs (peak-to-peak value)



0.7

0.8

V

IPAudio

(1)

Ptot Input voltages

ViY(p-p)

luminance input signal (peak-to-peak value)



1.4 / 1.0



V

ViU(p-p) / ViPB(p-p)

U / PB input signal (peak-to-peak value); note 2



−1.33 / +0.7



V

ViV(p-p) / ViPR(p-p)

V / PR input signal (peak-to-peak value); note 2



−1.05 / +0.7



V

Vo(IFVO)(p-p)

demodulated CVBS output (peak-to-peak value)



2.0



V

Vo(QSSO)(rms)

sound IF intercarrier output (RMS value)



100



mV

Vo(AMOUT)(rms)

demodulated AM sound output (RMS value)



250



mV

non-controlled audio output signals (RMS value)

1.0





V

Output signals

Vo(AUDIO)(rms)

(1)

Vo(CVBSO)(p-p)

selected CVBS output (peak-to-peak value)



2.0



V

Io(AGCOUT)

tuner AGC output current range

0



1

mA

VoRGB(p-p)

RGB output signal amplitudes (peak-to-peak value)



1.2



V

IoHOUT

horizontal output current

10





mA

IoVERT

vertical output current (peak-to-peak value)



1



mA

IoEWD

EW drive output current





1.2

mA

Note 1. The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximum signal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is 2 Vrms. 2. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation. 2003 Nov 11

10

CONFIDENTIAL

2003 Nov 11

CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP

IFVO/SVO/ CVBSI YSYNC CVBS2/Y2

VIFIN

AGCOUT

DVBO/IFVO/ FMRO DVBO/FMRO

SIFIN/DVBIN

11

CONFIDENTIAL

H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE

VIDEO FILTERS

VIDEO SWITCH VIDEO IDENT.

H/V

Y

C

SOUND PLL

SWO1 BL

R/PR B/PB

G/Y

B/PB

Ui Vi

L

SATURATION

U/V TINT

SKIN TONE

YUV

U/V DELAY

MODULATION

PEAKING SCAN VELOCITY

SAT

BRI

CON.

SCAVEM ON TEXT

G

B

GAMMA CONTROL

RGB MATRIX BLUE STRETCH BLACK STRETCH

RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.

BL R

R

CR

HP-OUT

DIGITAL SIGNAL PROCESSING FEATURES

R/PR G/Y (CVBSx/Yx) (Cx)

Yi

R

AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs

L

LS-OUT

RDS

I2S

µ-PROCESSOR AND TELETEXT DECODER

ADC/DAC

AUDIO SELECT

SCART/CINCH IN/OUT

Fig.1 Block diagram of the “Stereo” TV processor

EWD

EHTO BL

Vo Uo Yo

YUV INTERFACE

RGB/YPRPB INSERT

AM

YUV IN/OUT

V-DRIVE

GEOMETRY

& EAST-WEST

VERTICAL

Y DELAY ADJ.

DIGITAL 2H/4H COMB FILTER

DELAY LINE

DECODER REF

BASE-BAND

A/D CONVERTER ALL-STANDARD STEREO DECODER

PAL/SECAM/NTSC

DEEMPHASIS

SSIF

SVM

BCLIN BLKIN

BO

RO GO

I/Os

Versatile signal processor for low- and mid-range TV applications

HOUT

VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.

SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR

REFO

QSSO/AMOUT

Philips Semiconductors Preliminary specification

UOCIII series

BLOCK DIAGRAMS

2003 Nov 11

12

CONFIDENTIAL

CVBSO/ PIP

CVBS3/Y3 C2/C3 CVBS4/Y4 C4

IFVO/SVO/ CVBSI YSYNC CVBS2/Y2

VIFIN

AGCOUT

DVBO/IFVO/ FMRO DVBO/FMRO

SIFIN/DVBIN

H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE

VIDEO FILTERS

VIDEO SWITCH VIDEO IDENT.

H/V

Y

C

G/Y

SWO1 BL

R/PR B/PB

L

R

HP-OUT

RDS

SATURATION

SKIN TONE U/V TINT

SCAN VELOCITY MODULATION U/V DELAY

PEAKING

SAT

BRI

CON.

SCAVEM ON TEXT

G

B

GAMMA CONTROL

RGB MATRIX BLUE STRETCH BLACK STRETCH

RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.

BL R

DIGITAL SIGNAL PROCESSING FEATURES

µ-PROCESSOR AND TELETEXT DECODER

R/PR G/Y (CVBSx/Yx) (Cx)

B/PB

R

AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs

L

LS-OUT

Fig.2 Block diagram of the “AV-stereo” TV processor with audio DSP

EWD

EHTO BL

Vo Uo Yo Yi Vi Ui

YUV INTERFACE

RGB/YPRPB INSERT

I2S

YUV IN/OUT

V-DRIVE

GEOMETRY

& EAST-WEST

VERTICAL

Y DELAY ADJ.

DIGITAL 2H/4H COMB FILTER

DELAY LINE

ADC/DAC

DECODER REF

AM

AUDIO SELECT

BASE-BAND

DEEMPHASIS

SOUND PLL

SCART/CINCH IN/OUT

PAL/SECAM/NTSC

SSIF

CR

SVM

BCLIN BLKIN

BO

RO GO

I/Os

Versatile signal processor for low- and mid-range TV applications

HOUT

VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.

SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR

REFO

QSSO/AMOUT

Philips Semiconductors Preliminary specification

UOCIII series

2003 Nov 11

13

CONFIDENTIAL

CVBSO/ PIP

CVBS3/Y3 C2/C3 CVBS4/Y4 C4

IFVO/SVO/ CVBSI YSYNC CVBS2/Y2

VIFIN

AGCOUT

DVBO/IFVO/ FMRO DVBO/FMRO

SIFIN/DVBIN

H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE

VIDEO FILTERS

VIDEO SWITCH VIDEO IDENT.

H/V

Y

C

SWO1 BL

R/PR B/PB

RDS

SATURATION

SKIN TONE U/V TINT

SCAN VELOCITY MODULATION U/V DELAY

PEAKING

SAT

BRI

CON.

SCAVEM ON TEXT

G

B

GAMMA CONTROL

RGB MATRIX BLUE STRETCH BLACK STRETCH

RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC WHITE-P. ADJ.

BL R

DIGITAL SIGNAL PROCESSING FEATURES

µ-PROCESSOR AND TELETEXT DECODER

R/PR G/Y (CVBSx/Yx) (Cx)

B/PB

R

VOLUME CONTROL

L

LS-OUT

Fig.3 Block diagram of the “AV-stereo” TV processor without audio DSP

EWD

EHTO BL

Vo Uo Yo Yi Vi Ui

YUV INTERFACE

RGB/YPRPB INSERT

YUV IN/OUT

V-DRIVE

GEOMETRY

& EAST-WEST

VERTICAL

2H/4H COMB FILTER Y DELAY ADJ.

DIGITAL

DELAY LINE

G/Y

AUDIO SELECT

DECODER REF

AM

BASE-BAND

DEEMPHASIS

SOUND PLL

SCART/CINCH IN/OUT

PAL/SECAM/NTSC

SSIF

CR

SVM

BCLIN BLKIN

BO

RO GO

I/Os

Versatile signal processor for low- and mid-range TV applications

HOUT

VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.

SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR

REFO

QSSO/AMOUT

Philips Semiconductors Preliminary specification

UOCIII series

2003 Nov 11

14

CONFIDENTIAL

CVBSO/PIP

YSYNC

C4

CVBS3/Y3 C2/C3 CVBS4/Y4

CVBS2/Y2

IFVO/SVO/ CVBSI

HOUT

G/Y SWO1 BL

R/PR B/PB

BL

G/Y

YI

VI

(Cx)

B/PB R/PR

UI

(CVBS/Yx)

VO UO YO

YUV INTERFACE

RGB/YUV/YPRPB INSERT

PEAKING SCAN VELOCITY MODULATION U/V DELAY

Fig. 4 Block diagram of the “Mono” TV processor

V-DRIVE (EWD) EHTO

AND DRIVE

U/V

Y

DELAY LINE

BASE-BAND

YUV

R

G

B

BL

GAMMA CONTROL

SKIN TONE U/V TINT SATURATION BLACK STRETCH

CONTR/BRIGHTN OSD/TEXT INSERT BLUE STRETCH CCC WHITE-P. ADJ.

COR

SCAVEM ON TEXT

BLKIN

BCLIN

BO

GO

RO

SVM

Versatile signal processor for low- and mid-range TV applications

(REFO)

V

GEOMETRY

VERTICAL + EW

COMB FILTER Y DELAY ADJ.

4H/2H

DIGITAL

REF

RDS

DIGITAL SIGNAL PROCESSING FEATURES

µ-PROCESSOR AND TELETEXT DECODER

YUV IN/OUT

H-DRIVE

H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT

VIDEO FILTERS

VIDEO IDENT.

VIDEO SWITCH

DECODER

PAL/SECAM/NTSC

AUDOUT/AMOUT

VIFIN

VISION IF/AGC/AFC REF PLL DEMOD. DVB MIXER GROUP DELAY SOUND TRAP

(SSIF)

AGCOUT

QSSO/AMOUT AUDEEM

DVBO/IFVO FMRO

SIFIN/DVBIN

(AVL) SOUND PLL DEEMPHASIS AUDIO SWITCH AVL VOLUME CONTROL

AUDIO3 AUDIO2

SWITCH

AUDIO5 AUDIO4

QSS SOUND IF AGC QSS MIXER AM DEMODULATOR

I/Os

Philips Semiconductors Preliminary specification

UOCIII series

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

1

1

128

128

128

ground

VSSC4

2

2

2

127

127

127

ground

VDDC4

3

3

3

126

126

126

digital supply to SDACs (1.8V)

VDDA3(3.3V)

4

4

4

125

125

125

supply (3.3 V)

VREF_POS_LSL

5





124





positive reference voltage SDAC (3.3 V)

VREF_NEG_LSL+HPL

6





123





negative reference voltage SDAC (0 V)

VREF_POS_LSR+HPR

7





122





positive reference voltage SDAC (3.3 V)

VREF_NEG_HPL+HPR

8





121





negative reference voltage SDAC (0 V)

VREF_POS_HPR

9





120





positive reference voltage SDAC (3.3 V)

XTALIN

10

10

10

119

119

119

crystal oscillator input

XTALOUT

11

11

11

118

118

118

crystal oscillator output

VSSA1

12

12

12

117

117

117

ground

VGUARD/SWIO

13

13

13

116

116

116

V-guard input / I/O switch (e.g. 4 mA current sinking capability for direct drive of LEDs)

DECDIG

14

14

14

115

115

115

decoupling digital supply

VP1

15

15

15

114

114

114

1st supply voltage TV-processor (+5 V)

PH2LF

16

16

16

113

113

113

phase-2 filter

PH1LF

17

17

17

112

112

112

phase-1 filter

GND1

18

18

18

111

111

111

ground 1 for TV-processor

SECPLL

19

19

19

110

110

110

SECAM PLL decoupling

DECBG

20

20

20

109

109

109

bandgap decoupling

EWD/AVL (1)

21

21

21

108

108

108

East-West drive output or AVL capacitor

15

CONFIDENTIAL

Preliminary specification

MONO

1

DESCRIPTION

UOCIII series

AV STEREO NO AUDIO DSP

VSSP2

SYMBOL

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

“STANDARD” VERSION STEREO + AV STEREO

2003 Nov 11

PINNING OF THE VARIOUS VERSIONS

MONO

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

22

22

107

107

107

vertical drive B output

VDRA

23

23

23

106

106

106

vertical drive A output

VIFIN1

24

24

24

105

105

105

IF input 1

VIFIN2

25

25

25

104

104

104

IF input 2

VSC

26

26

26

103

103

103

vertical sawtooth capacitor

IREF

27

27

27

102

102

102

reference current input

GNDIF

28

28

28

101

101

101

ground connection for IF amplifier

SIFIN1/DVBIN1 (2)

29

29

29

100

100

100

SIF input 1 / DVB input 1

SIFIN2/DVBIN2 (2)

30

30

30

99

99

99

SIF input 2 / DVB input 2

AGCOUT

31

31

31

98

98

98

tuner AGC output

EHTO

32

32

32

97

97

97

EHT/overvoltage protection input

AVL/SWO/SSIF/ REFO/REFIN (2)(3)

33

33

33

96

96

96

Automatic Volume Levelling / switch output / sound IF input / subcarrier reference output / external reference signal input for I signal mixer for DVB operation

AUDIOIN5





34





95

audio 5 input

AUDIOIN5L

34

34



95

95



audio-5 input (left signal)

AUDIOIN5R

35

35



94

94



audio-5 input (right signal)

AUDOUTSL

36

36



93

93



audio output for SCART/CINCH (left signal)

AUDOUTSR

37

37



92

92



audio output for SCART/CINCH (right signal)

38

38

38

91

91

91

decoupling sound demodulator

39

39

39

90

90

90

QSS intercarrier output / AM output / deemphasis (front-end audio out)

40

40

40

89

89

89

ground 2 for TV processor

DECSDEM QSSO/AMOUT/AUDEEM GND2

(2)

Preliminary specification

AV STEREO NO AUDIO DSP

22

DESCRIPTION

UOCIII series

STEREO + AV STEREO

16

CONFIDENTIAL

VDRB

SYMBOL

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

“STANDARD” VERSION

MONO

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

41

88

88

88

IF-PLL loop filter

42

42

42

87

87

87

AGC sound IF / internal-external AGC for DVB applications

43

43

43

86

86

86

Digital Video Broadcast output / IF video output / FM radio output

44

44



85

85



Digital Video Broadcast output / FM radio output

VCC8V

45

45

45

84

84

84

8 Volt supply for audio switches

AGC2SIF

46





83





AGC capacitor second sound IF

VP2

47

47

47

82

82

82

2nd supply voltage TV processor (+5 V)

IFVO/SVO/CVBSI (2)

48

48

48

81

81

81

IF video output / selected CVBS output / CVBS input

AUDIOIN4





49





80

audio 4 input

AUDIOIN4L

49

49



80

80



audio-4 input (left signal)

AUDIOIN4R

50

50



79

79



audio-4 input (right signal)

CVBS4/Y4

51

51

51

78

78

78

CVBS4/Y4 input

C4

52

52

52

77

77

77

chroma-4 input





53





76

audio 2 input

53

53



76

76



audio 2 input (left signal) / sound IF input

AUDIOIN2R

54

54



75

75



audio 2 input (right signal)

CVBS2/Y2

55

55

55

74

74

74

CVBS2/Y2 input

AUDIOIN3





56





73

audio 3 input

AUDIOIN3L

56

56



73

73



audio 3 input (left signal)

AUDIOIN3R

57

57



72

72



audio 3 input (right signal)

CVBS3/Y3

58

58

58

71

71

71

CVBS3/Y3 input

C2/C3

59

59

59

70

70

70

chroma-2/3 input

SIFAGC/DVBAGC (2) DVBO/IFVO/FMRO

17

CONFIDENTIAL

DVBO/FMRO

(2)

(2)

AUDIOIN2 AUDIOIN2L/SSIF

(3)

Preliminary specification

AV STEREO NO AUDIO DSP 41

PLLIF

DESCRIPTION

UOCIII series

STEREO + AV STEREO 41

SYMBOL

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

“STANDARD” VERSION

MONO

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

62



69

67



audio output for audio power amplifier (left signal)

AUDOUTLSR

61

63



68

66



audio output for audio power amplifier (right signal)

AUDOUT/AMOUT/FMOUT





62





67

audio output / AM output / FM output, volume controlled

AUDOUTHPL

62





67





audio output for headphone channel (left signal)

AUDOUTHPR

63





66





audio output for headphone channel (right signal)

CVBSO/PIP

64

64

64

65

65

65

CVBS / PIP output

SVM

65

65

65

64

64

64

scan velocity modulation output

FBISO/CSY

66

66

66

63

63

63

flyback input/sandcastle output or composite H/V timing output

HOUT

67

67

67

62

62

62

horizontal output

VSScomb

68

68

68

61

61

61

ground connection for comb filter

VDDcomb

69

69

69

60

60

60

supply voltage for comb filter (5 V)

VIN (R/PRIN2/CX)

70

70

70

59

59

59

V-input for YUV interface (2nd R input / PR input or CX input)

UIN (B/PBIN2)

71

71

71

58

58

58

U-input for YUV interface (2nd B input / PB input)

YIN (G/YIN2/CVBS-YX)

72

72

72

57

57

57

Y-input for YUV interface (2nd G input / Y input or CVBS/YX input))

YSYNC

73

73

73

56

56

56

Y-input for sync separator

YOUT

74

74

74

55

55

55

Y-output (for YUV interface)

UOUT (INSSW2)

75

75

75

54

54

54

U-output for YUV interface (2nd RGB / YPBPR insertion input)

VOUT (SWO1)

76

76

76

53

53

53

V-output for YUV interface (general purpose switch output)

INSSW3

77

77

77

52

52

52

3rd RGB / YPBPR insertion input

R/PRIN3

78

78

78

51

51

51

3rd R input / PR input

G/YIN3

79

79

79

50

50

50

3rd G input / Y input

B/PBIN3

80

80

80

49

49

49

3rd B input / PB input

Preliminary specification

AV STEREO NO AUDIO DSP

60

DESCRIPTION

UOCIII series

STEREO + AV STEREO

18

CONFIDENTIAL

AUDOUTLSL

SYMBOL

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

“STANDARD” VERSION

MONO

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

81

48

48

48

ground 3 for TV-processor

VP3

82

82

82

47

47

47

3rd supply for TV processor

BCLIN

83

83

83

46

46

46

beam current limiter input

BLKIN

84

84

84

45

45

45

black current input

RO

85

85

85

44

44

44

Red output

GO

86

86

86

43

43

43

Green output

BO

87

87

87

42

42

42

Blue output

VDDA1

88

88

88

41

41

41

analog supply for TCG µ-Controller and digital supply for TV-processor (+3.3 V)

VREFAD_NEG

89

89

89

40

40

40

negative reference voltage (0 V)

VREFAD_POS

90

90

90

39

39

39

positive reference voltage (3.3 V)

VREFAD

91





38





reference voltage for audio ADCs (3.3/2 V)

GNDA

92

92

92

37

37

37

ground

VDDA(1.8V)

93

93

93

36

36

36

analogue supply for audio ADCs (1.8 V)

VDDA2(3.3)

94

94

94

35

35

35

supply voltage SDAC (3.3 V)

VSSadc

95

95

95

34

34

34

ground for video ADC and PLL

VDDadc(1.8)

96

96

96

33

33

33

supply voltage video ADC and PLL

INT0/P0.5

97

97

97

32

32

32

external interrupt 0 or port 0.5 (4 mA current sinking capability for direct drive of LEDs)

P1.0/INT1

98

98

98

31

31

31

port 1.0 or external interrupt 1

P1.1/T0

99

99

99

30

30

30

port 1.1 or Counter/Timer 0 input

VDDC2

100

100

100

29

29

29

digital supply to core (1.8 V)

VSSC2

101

101

101

28

28

28

ground

Preliminary specification

AV STEREO NO AUDIO DSP 81

DESCRIPTION

UOCIII series

STEREO + AV STEREO 81

19

CONFIDENTIAL

GND3

SYMBOL

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

“STANDARD” VERSION

MONO

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO



27





port 0.4 or I2S word select



102

102



27

27

port 0.4

103





26





port 0.3 or I2S clock



103

103



26

26

port 0.3

104





25





port 0.2 or I2S digital output 2



104

104



25

25

port 0.2

105





24





port 0.1 or I2S digital output 1



105

105



24

24

port 0.1

106





23





port 0.0 or I2S digital input 1 or I2S digital output



106

106



23

23

port 0.0

P1.3/T1

107

107

107

22

22

22

port 1.3 or Counter/Timer 1 input

P1.6/SCL

108

108

108

21

21

21

port 1.6 or I2C-bus clock line

P1.7/SDA

109

109

109

20

20

20

port 1.7 or I2C-bus data line

VDDP(3.3V)

110

110

110

19

19

19

supply to periphery and on-chip voltage regulator (3.3 V)

P2.0/TPWM

111

111

111

18

18

18

port 2.0 or Tuning PWM output

P2.1/PWM0

112

112

112

17

17

17

port 2.1 or PWM0 output

P2.2/PWM1

113

113

113

16

16

16

port 2.2 or PWM1 output

P2.3/PWM2

114

114

114

15

15

15

port 2.3 or PWM2 output

P3.0/ADC0

115

115

115

14

14

14

port 3.0 or ADC0 input

P3.1/ADC1

116

116

116

13

13

13

port 3.1 or ADC1 input

VDDC1

117

117

117

12

12

12

digital supply to core (+1.8 V)

DECV1V8

118

118

118

11

11

11

decoupling 1.8 V supply

P0.4 P0.3/I2SCLK

P0.2/I2SDO2 P0.2 P0.1/I2SDO1 P0.1 20

CONFIDENTIAL

P0.3

P0.0/I2SDI1/O P0.0

Preliminary specification

AV STEREO NO AUDIO DSP −

P0.4/I2SWS

DESCRIPTION

UOCIII series

STEREO + AV STEREO 102

SYMBOL

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

“STANDARD” VERSION

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

STEREO + AV STEREO

AV STEREO NO AUDIO DSP

MONO

21

CONFIDENTIAL

P3.2/ADC2

119

119

119

10

10

10

port 3.2 or ADC2 input

P3.3/ADC3

120

120

120

9

9

9

port 3.3 or ADC3 input

VSSC/P

121

121

121

8

8

8

digital ground for µ-Controller core and periphery

P2.4/PWM3

122

122

122

7

7

7

port 2.4 or PWM3 output

P2.5/PWM4

123

123

123

6

6

6

port 2.5 or PWM4 output

VDDC3

124

124

124

5

5

5

digital supply to core (1.8V)

VSSC3

125

125

125

4

4

4

ground

P1.2/INT2

126

126

126

3

3

3

port 1.2 or external interrupt 2

P1.4/RX

127

127

127

2

2

2

port 1.4 or UART bus

P1.5/TX

128

128

128

1

1

1

port 1.5 or UART bus

SYMBOL

DESCRIPTION

Philips Semiconductors

“FACE DOWN” VERSION

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

“STANDARD” VERSION

Note 1. The function of this pin can be chosen by means of the AVLE bit. 2. The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in table 4. 3. With the ESSIF bit the SSIF input can be selected either on pin 33 or pin 53. For the “face down” versions these pin numbers are 96 and 76 respectively.

Preliminary specification

UOCIII series

ANALOGUE TV MODE IC MODE DVB MODE

FM-PLL MODE (QSS = 0) FM DEMODULATION

FUNCTION IFA/IFB/IFC bits

000/001/010/011/100/110

0

0



FMI bit AVLE bit CMB2/CMB1/CMB0 bits

0

010/011

100

101/111

0



1

1

0

1

0



1

1

0

1

0

1

0

000/001/010/011/101/110

22

CONFIDENTIAL



AM bit

FM RADIO MODE

QSS-FM DEMODULATION

QSS/AM DEMODULATION

101/111

FMR bit

Standard

QSS MODE (QSS = 1)



0

1

0



1



Face-down

pin 21

pin 108

pin 29

pin 100

DVBIN1



SIFIN1

SIFIN1

pin 30

pin 99

DVBIN2



SIFIN2

SIFIN2

pin 33

(1)

pin 96

(1)

AVL

EWD

SWO

REFIN

AVL

EWD

SWO/ SSIF/ REFO

AVL/ SWO/ SSIF/ REFO

AVL

EWD

SWO/SSIF/REFO

AVL/SWO/SSIF/ REFO

QSSO

QSSO

AVL

SWO/ SSIF/ REFO

EWD

AVL/ SWO/ SSIF/ REFO

AVL

SWO/ SSIF/ REFO

EWD

AVL/ SWO/ SSIF/ REFO

pin 39

pin 90



AUDEEM

pin 42

pin 87

DVBAGC



SIFAGC

SIFAGC

DVBO

IFVO

IFVO

FMRO

pin 43

(2)

pin 44

(2)

pin 86

(2)

pin 85

(2)

AMOUT

AMOUT

AUDEEM

AUDEEM

DVBO





FMRO

pin 48 (3)

pin 81 (3)

SVO/CVBSI

IFVO/SVO/CVBSI

IFVO/SVO/CVBSI

IFVO/SVO/CVBSI

pin 62 (4)

pin 67 (4)

AUDOUT

AUDOUT

AUDOUT AMOUT AUDOUT AMOUT

AUDOUT

Philips Semiconductors

Pin functions for various modes of operation

Versatile signal processor for low- and mid-range TV applications

2003 Nov 11

Table 4

AUDOUT

2. The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H. 3. The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H. 4. This functionality is only valid for the mono versions. In the “stereo” and “AV-stereo” versions this pin has the function of audio output for the headphone channel (left signal).

UOCIII series

1. The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH.

Preliminary specification

Note

Philips Semiconductors

Preliminary specification

97 INT0/P0.5

101 VSSC2 100 VDDC2 99 P1.1/T0 98 P1.O/INT1

P1.7/SDA P1.6/SCL P1.3/T1 107 106 P0.0/I2SDI1 P0.1/I2SDO1 105 104 P0.2/I2SDO2 103 P0.3/I2SCLK 102 P0.4/I2SWS

P2.2/PWM1

P2.1/PWM0 P2.0/PMW VDDP(3.3V)

UOCIII series

113 112 111 110 109 108

118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2

127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2

128 P1.5/TX

Versatile signal processor for low- and mid-range TV applications

VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96

VSSP2 1 VSSC4 2 VDDC4 3 VDDA3(3.3V) 4 VREF_POS_LSL 5 VREF_NEG_LSL+LSR 6 VREF_POS_LSR+HPL 7 VREF_NEG_HPL+HPR 8 VREF_POS_HPR 9

91 VREFAD 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO

XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20

77 76 75 74 73 72 71 70 69 68 67 66 65 60 61 62 63 CVBSO/PIP 64

59

C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR

52 AUDIOIN2L 53 AUDIOIN2R/SSIF 54 CVBS2/Y2 55 AUDIOIN3L 56 AUDIOIN3R 57 CVBS3/Y3 58

51

49 50 AUDIOIN4L

AUDIOIN4R CVBS4/Y4 C4

47 48

43 44 45 46

AGC2SIF VP2 SVO/IFOUT/CVBSI

PLLIF

SIFAGC/DVBAGC DVBO//IFVO/FMRO DVBO/FMRO VCC8V

GND2

AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM

41 42

QFP-128 0.8mm pitch “standard version” 33 34

AGCOUT EHTO

39 40

GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2

21 22 23 24 25 26 27 28 29 30 31 32

82 VP3 81 GND3 80 B/PB-3 79 G/Y-3 78 R/PR-3

35 36 37 38

AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF

RO BLKIN 84 83 BCLIN 85

Fig.5 Pin configuration “stereo” and “AV-stereo” versions with Audio DSP

2003 Nov 11

23

CONFIDENTIAL

INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM

Philips Semiconductors

Preliminary specification

85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

CVBS3/Y3 C2/C3 59 - 60 - 61 AUDOUTLSL 62 AUDOUTLSR 63 CVBSO/PIP 64

AUDIOIN3L

AUDIOIN3R

AUDIOIN2R CVBS2/Y2

52 53 54 55 56 57 58 AUDIOIN2L/SSIF

51

49 50 AUDIOIN4L

AUDIOIN4R CVBS4/Y4 C4

AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM AMOUT/QSSO/AUDEEM

47 48

QFP-128 0.8mm pitch “standard version” 33 34

11 12 13 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20 AVL/EWD 21 VDRB 22 VDRA 23 VIFIN1 24 VIFIN2 25 VSC 26 IREF 27 GNDIF 28 DVBIN1/SIFIN1 29 DVBIN2/SIFIN2 30 AGCOUT 31 EHTO 32

Fig.6 Pin configuration of “AV stereo” versions without Audio DSP

2003 Nov 11

97 INT0/P0.5

P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1

P0.2

104 103 102 101 100

107 P1.3/T1 106 P0.0 105 P0.1

P1.7/SDA P1.6/SCL

P2.2/PWM1

P2.1/PWM0 P2.0/PMW VDDP(3.3V)

113 112 111 110 109 108

VSSC1/P P3.3/ADC3 119 P3.2/ADC2 118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 114 P2.3/PWM2

VDDC3 P2.5/PWM4 P2.4/PWM3

123 122 121 120

124

9 10

VP2 SVO/IFOUT/CVBSI

XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG

41 SIFAGC/DVBAGC 42 DVBO//IFVO/FMRO 43 - 44 VCC8V 45 - 46

-

91 90 VREFAD_POS 89 VREFAD_NEG 88 VDDA1(3.3V.) 87 BO 86 GO

PLLIF

-

3 4 5 6 7 8

39 40

-

VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 96

GND2

VDDA3(3.3V) -

UOCIII series

1 2

35 36 37 38

VSSP2 VSSC4 VDDC4

127 P1.4/RX 126 P1.2/INT2 125 VSSC3

128 P1.5/TX

Versatile signal processor for low- and mid-range TV applications

24

CONFIDENTIAL

B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM

Philips Semiconductors

Preliminary specification

VSSP2 VSSC4 VDDC4 VDDA3(3.3V) -

97 INT0/P0.5

P0.3 P0.4 VSSC2 VDDC2 99 P1.1/T0 98 P1.O/INT1

P0.2

104 103 102 101 100

107 P1.3/T1 106 P0.0 105 P0.1

P1.7/SDA P1.6/SCL

P2.2/PWM1

P2.1/PWM0 P2.0/PMW VDDP(3.3V)

UOCIII series

113 112 111 110 109 108

118 DECV1V8 117 VDDC1(1.8) 116 P3.1/ADC1 P3.0/ADC0 115 P2.3/PWM2 114

127 P1.4/RX 126 P1.2/INT2 125 VSSC3 124 VDDC3 123 P2.5/PWM4 122 P2.4/PWM3 121 VSSC1/P 120 P3.3/ADC3 119 P3.2/ADC2

128 P1.5/TX

Versatile signal processor for low- and mid-range TV applications

VDDadc(1.8) 95 VSSadc 94 VDDA2(3.3V) 93 VDDA(1.8V) 92 GNDA 91 90 VREFAD_POS 89 VREFAD_NEG 96

1 2 3 4 5 6 7 8

88 VDDA1(3.3V.) 87 BO 86 GO

9 XTALIN 10 XTALOUT 11 VSSA1 12 VGUARD/SWIO 13 DECDIG 14 VP1 15 PH2LF 16 PH1LF 17 GND1 18 SECPLL 19 DECBG 20

25

CONFIDENTIAL

60 61 AUDOUT/AMOUT 62 - 63 CVBSO/PIP 64 -

52 AUDIOIN2 53 - 54 CVBS2/Y2 55 AUDIOIN3 56 - 57 CVBS3/Y3 58 C2/C3 59

51

AUDIOIN4 CVBS4/Y4 C4

47 48 VP2 SVO/IFOUT/CVBSI

49 50

43 44 45 46

PLLIF

41 42

SIFAGC/DVBAGC DVBO//IFVO/FMRO VCC8V -

39 40 GND2

AVL/SWO/SSIF/ REFIN/REFOUT AUDIOIN5 -

Fig.7 Pin configuration “mono” versions

2003 Nov 11

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

QFP-128 0.8mm pitch “standard version” 33 34

AGCOUT EHTO

DECSDEM AMOUT/QSSO/AUDEEM

GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2

21 22 23 24 25 26 27 28 29 30 31 32

80

35 36 37 38

AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF

85 RO 84 BLKIN 83 BCLIN 82 VP3 81 GND3 B/PB-3 G/Y-3 R/PR-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN (B/PB-2) VIN(R/PR-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM

Philips Semiconductors

Preliminary specification

97 EHTO

99 DVBIN2/SIFIN2 98 AGCOUT

IREF GNDIF DVBIN1/SIFIN1

VIFIN1 VIFIN2 VSC

105 104 103 102 101 100

107 VDRB 106 VDRA

DECBG AVL/EWD

PH1LF GND1 SECPLL

DECDIG VP1 PH2LF

UOCIII series

115 114 113 112 111 110 109 108

119 XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO

122 VREF_POS_LSR+HPL 121 VREF_NEG_HPL+HPR 120 VREF_POS_HPR

127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 VREF_POS_LSL 123 VREF_NEG_LSL+LSR

128 VSSP2

Versatile signal processor for low- and mid-range TV applications

AVL/SWO/SSIF/ 96 REFIN/REFOUT

P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8

95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2

P3.3/ADC3

88 PLLIF

9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20

QFP-128 0.8 mm pitch “face down version” VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36

INT0/P0.5

74 73 72 71 70 69 68 67 66 65

CVBS2/Y2 AUDIOIN3L AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR CVBSO/PIP

VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64

VSSC2 VDDC2 P1.1/T0 P1.O/INT1

INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58

P0.4/I2SWS

VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51

P0.3/I2SCLK

VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46

P0.2/I2SDO2

21 22 23 24 25 26 27 28 29 30 31 32

84 VCC8V 83 AGC2SIF 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R

GNDA 37 VREFAD 38 VREFAD_POS 39 VREFAD_NEG 40

P1.6/SCL P1.3/T1 P0.0/I2SDI1 P0.1/I2SDO1

87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 DVBO/FMRO

Fig.8 Pin configuration “stereo” and “AV-stereo” versions with Audio DSP

2003 Nov 11

26

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

97 EHTO

99 DVBIN2/SIFIN2 98 AGCOUT

IREF GNDIF DVBIN1/SIFIN1

VIFIN1 VIFIN2 VSC

105 104 103 102 101 100

107 VDRB 106 VDRA

DECBG AVL/EWD

PH1LF GND1 SECPLL

DECDIG VP1 PH2LF

UOCIII series

115 114 113 112 111 110 109 108

XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO

120 -

119

VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 123 122 121 127

128

VSSP2

Versatile signal processor for low- and mid-range TV applications

AVL/SWO/SSIF/ 96 REFIN/REFOUT

P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8

95 AUDIOIN5L 94 AUDIOIN5R 93 AUDOUTSL 92 AUDOUTSR 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2

P3.3/ADC3

88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4L 79 AUDIOIN4R 78 CVBS4/Y4 77 C4 76 AUDIOIN2L/SSIF 75 AUDIOIN2R 74 73 72 71 70 69 68 67 66 65 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61 HOUT 62 FBISO/CSY 63 SVM 64

INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58

VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51

VREFAD_POS 39 VREFAD_NEG 40 VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46

VDDA2(3.3V) 35 VDDA(1.8V) 36 GNDA 37 - 38

QFP-128 0.8mm pitch “face down version” VDDadc(1.8) 33 VSSadc 34

9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL 21 P1.3/T1 22 P0.0 23 P0.1 24 P0.2 25 P0.3 26 P0.4 27 VSSC2 28 VDDC2 29 P1.1/T0 30 P1.O/INT1 31 INT0/P0.5 32

Fig.9 Pin configuration of “AV stereo” versions without Audio DSP

2003 Nov 11

27

CVBS2/Y2 AUDIOIN3L AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR CVBSO/PIP

Philips Semiconductors

Preliminary specification

97 EHTO

99 DVBIN2/SIFIN2 98 AGCOUT

IREF GNDIF DVBIN1/SIFIN1

VIFIN1 VIFIN2 VSC

105 104 103 102 101 100

107 VDRB 106 VDRA

DECBG AVL/EWD

PH1LF GND1 SECPLL

DECDIG VP1 PH2LF

UOCIII series

115 114 113 112 111 110 109 108

XTALIN 118 XTALOUT 117 VSSA1 116 VGUARD/SWIO

120 -

119

127 VSSC4 126 VDDC4 125 VDDA3(3.3V) 124 123 122 121 -

128 VSSP2

Versatile signal processor for low- and mid-range TV applications

AVL/SWO/SSIF/ 96 REFIN/REFOUT

P1.5/TX 1 P1.4/RX 2 P1.2/INT2 3 VSSC3 4 VDDC3 5 P2.5/PWM4 6 P2.4/PWM3 7 VSSC1/P 8

95 AUDIOIN5 94 93 92 91 DECSDEM 90 AMOUT/QSSO/AUDEEM 89 GND2

P3.3/ADC3

88 PLLIF 87 SIFAGC/DVBAGC 86 DVBO//IFVO/FMRO 85 84 VCC8V 83 82 VP2 81 SVO/IFOUT/CVBSI 80 AUDIOIN4 79 78 CVBS4/Y4 77 C4 76 AUDIOIN2 75 -

28

CONFIDENTIAL

HOUT 62 FBISO/CSY 63 SVM 64

INSSW3 52 VOUT(SWO1) 53 UOUT(INSW-2) 54 YOUT 55 YSYNC 56 YIN(G/Y-2/CVBS/Y-X) 57 UIN (B/PB-2) 58 VIN(R/PR-2/C-X) 59 VDDcomb 60 VSScomb 61

VP3 47 GND3 48 B/PB-3 49 G/Y-3 50 R/PR-3 51

VDDA1(3.3V.) 41 BO 42 GO 43 RO 44 BLKIN 45 BCLIN 46

39 40

37 38

GNDA VREFAD_POS VREFAD_NEG

Fig.10 Pin configuration “mono” versions

2003 Nov 11

74 73 72 71 70 69 68 67 66 65

QFP-128 0.8mm pitch “face down version” VDDadc(1.8) 33 VSSadc 34 VDDA2(3.3V) 35 VDDA(1.8V) 36

9 P3.2/ADC2 10 DECV1V8 11 VDDC1(1.8) 12 P3.1/ADC1 13 P3.0/ADC0 14 P2.3/PWM2 15 P2.2/PWM1 16 P2.1/PWM0 17 P2.0/PMW 18 VDDP(3.3V) 19 P1.7/SDA 20 P1.6/SCL 21 P1.3/T1 22 P0.0 23 P0.1 24 P0.2 25 P0.3 26 P0.4 27 VSSC2 28 VDDC2 29 P1.1/T0 30 P1.O/INT1 31 INT0/P0.5 32

CVBS2/Y2 AUDIOIN3 CVBS3/Y3 C2/C3 AUDOUT/AMOUT CVBSO/PIP

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

FUNCTIONAL DESCRIPTION OF THE 80C51 The functionality of the micro-controller used on this device is described here with reference to the industry standard 80C51 micro-controller. A full description of its functionality can be found in the 80C51 based 8-bit micro-controllers - Philips Semiconductors (ref. IC20). Features of the 80c51 • 80C51 micro-controller core standard instruction set and timing • 0.4883µs machine cycle (Xtal frequency 24.576MHz) • Maximum 256Kx8bit Flash Program ROM • Maximum of 8Kx8bit Auxiliary RAM • 12-Level Interrupt Controller for individual enable/disable with two level priority Fig.11 ROM Bank switching memory map

• Two 16-bit Timer/Counter registers • Additional 24-bit Timer (16-bit timer with 8-bit pre-scaler) • WatchDog Timer

RAM Organisation The Internal Data RAM is organised into two areas, Data Memory and Special Function Registers (SFRs) as shown in Fig.12.

• Auxiliary RAM Page Pointer • 16-bit Data pointer • Stand-by, IDLE and Power Down (PD) modes • 24 General I/O via individual addressable controls • Five 6-bit Pulse Width Modulator (PWM) outputs for control of TV analogue signals

Internal RAM : “I-Data” FF H

• One 14-bit PWM for Voltage Synthesis tuning control

128B RAM only Indirect addressing

• 8-bit ADC with 4 multiplexed inputs • High-speed

I 2C

for ISP (up to 1.2 Mb/s)

RAM

80 H

30..7F H

20..2F H Bit-addressable space 18..1F H Register-Bank3

Lower 128 Byte RAM Direct & Indirect addressing

• Universal Asynchronous Receiver Transmitter (UART)

Special Function Registers = extension method for 80c51

7F H

• Remote Control Pre-processor (RCP) 00 H

10..17 H Register-Bank2

Register-Bank select bits in PSW

R-Bank

08..0F H Register-Bank1

R7 R6 R5 R4 R3 R2 R1 R0

00..07 H Register-Bank0

• Different addressing method for upper 128 Bytes accesses RAM or SFR

Memory Organisation The device has the capability of a maximum of 256K Bytes of PROGRAM ROM and 8K Bytes of AUX DATA RAM for internally.

Fig.12 Internal Data Memory

ROM Organisation The 256K is arranged in eight banks of 32K. One of the 32K banks is common and is always addressable. The other banks (Bank0 to Bank6) can be accessed by selecting the right bank via the SFR ROMBK bits 2/1/0.

2003 Nov 11

128B SFR only Direct addressing

DATA MEMORY The Data memory is 256 x 8-bits and occupies the address range 00 to FF Hex when using Indirect addressing and 00 to 7F Hex when using direct addressing. The SFRs occupy the address range 80 Hex to FF Hex and are accessible using Direct addressing only. The lower 128 Bytes of Data memory are mapped as shown in Fig.12. The lowest 32 bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. The upper 128 bytes are not allocated for any special area or functions. 29

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications SFR MEMORY The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and display control, etc. These registers can only be accessed by direct addressing.

ADD

R/W

Names

UOCIII series Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 5.

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

80H

R/W

P0

Reserved

Reserved

P0

P0

P0

P0

P0

P0

81H

R/W

SP

SP

SP

SP

SP

SP

SP

SP

SP

82H

R/W

DPL

DPL

DPL

DPL

DPL

DPL

DPL

DPL

DPL

83H

R/W

DPH

DPH

DPH

DPH

DPH

DPH

DPH

DPH

DPH

84H

R/W

IEN1

-

-

-

EX2

ERDS

EUART

ET2PR

EBUSY

85H

R/W

IP1

-

-

-

PX2

PRDS

PUART

PT2PR

PBUSY

86H

R/W

RCP1

DAT

DAT

DAT

DAT

DAT

DAT

DAT

DAT

87H

R/W

PCON

SMOD

ARD

RFI

WLE

GF1

GF0

PD

IDL

88H

R/W

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

89H

R/W

TMOD

GATE

C/T

M1

M0

GATE

C/T

M1

M0

8AH

R/W

TL0

TL0

TL0

TL0

TL0

TL0

TL0

TL0

TL0

8BH

R/W

TL1

TL1

TL1

TL1

TL1

TL1

TL1

TL1

TL1

8CH

R/W

TH0

TH0

TH0

TH0

TH0

TH0

TH0

TH0

TH0

8DH

R/W

TH1

TH1

TH1

TH1

TH1

TH1

TH1

TH1

TH1

8EH

R

RCP3

RA

RA

RA

RA

RA

RA

RA

RA

8FH

R

RCP4

RB

RB

RB

RB

RA

RA

RA

RA

90H

R/W

P1

P1

P1

P1

P1

P1

P1

P1

P1

91H

R/W

TP2L

TP2L

TP2L

TP2L

TP2L

TP2L

TP2L

TP2L

TP2L

92H

R/W

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

93H

R/W

TP2PR

TP2PR

TP2PR

TP2PR

TP2PR

TP2PR

TP2PR

TP2PR

TP2PR

94H

R/W

TP2CRL

-

-

-

-

-

-

TP2CRL

TP2CRL

95H

R/W

RCP2

-

-

-

-

DAT

DAT

DAT

DAT

96H

R/W

P0CFGA

Reserved

Reserved

P0CFGA

P0CFGA

P0CFGA

P0CFGA

P0CFGA

P0CFGA

97H

R/W

P0CFGB

Reserved

Reserved

P0CFGB

P0CFGB

P0CFGB

P0CFGB

P0CFGB

P0CFGB

98H

R/W

SADB

SSD_ON

-

-

DC_COMP

SAD

SAD

SAD

SAD

99H

R/W

S0CON

SM

SM

SM

REN

TB8

RB8

TI

RI

9AH

R/W

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

9BH

R

RCP5

RB

RB

RB

RB

RB

RB

RB

RB

9CH

R

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

9DH

R

TP2CH

TP2CH

TP2CH

TP2CH

TP2CH

TP2CH

TP2CH

TP2CH

TP2CH

9EH

R/W

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

9FH

R/W

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

2003 Nov 11

30

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ADD

R/W

Names

UOCIII series

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Reserved

Reserved

P2

P2

P2

P2

P2

P2

A0H

R/W

P2

A1H

R/W

TXT31

0

CC_TXT B

ACTIVE PAGE

1V8GUARD

GPF

GPF

GPF

GPF

A2H

R

TXT32

GPF

9FF

9FF

9FF

9FF

9FF

9FF

9FF

A3H

R

TXT33

BFE

BFE

BFE

BFE

BFE

BFE

BFE

BFE

A4H

R

TXT34

BFE

BFE

BFE

BFE

BFE

BFE

BFE

BFE

A5H

R/W

Video_process

-

-

-

-

-

-

DW_PA

DW_PA

A6H

R/W

P2CFGA

Reserved

Reserved

P2CFGA

P2CFGA

P2CFGA

P2CFGA

P2CFGA

P2CFGA

A7H

R/W

P2CFGB

Reserved

Reserved

P2CFGB

P2CFGB

P2CFGB

P2CFGB

P2CFGB

P2CFGB

A8H

R/W

IE

EA

ES2

ECC

EDET

ET1

EX1

ET0

EX0

A9H

R/W

TXT23

NOT B

NOT B

NOT B

NOT B

East/West B

DRCS B ENABLE

BS B

BS B

AAH

R/W

TXT24

BKGND OUT B

BKGND IN B

CORB OUT B

CORB IN B

TEXT OUT B

TEXT IN B

PICTURE ON OUT B

PICTURE ON IN B

ABH

R/W

TXT25

BKGND OUT B

BKGND IN B

CORB OUT B

CORB IN B

TEXT OUT B

TEXT IN B

PICTURE ON OUT B

PICTURE ON IN B

ACH

R/W

TXT26

EXTENDED DRCS

TRANS B

0

0

SHADOW ENABLE B

BOX ON 24 B

BOX ON 1-23 B

BOX ON 0B

ADH

R/W

TXT28

DISPLAY BANK B

DISPLAY BANK B

DISPLAY BANK B

DISPLAY BANK B

PAGE B

PAGE B

PAGE B

PAGE B

AEH

R

ADJUST_E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

AFH

R

ADJUST_E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

B0H

R/W

P3

Reserved

Reserved

Reserved

Reserved

P3

P3

P3

P3

B1H

R/W

TXT27

-

-

-

-

RDS ON

SCR B

SCR B

SCR B

B2H

R/W

TXT18

NOT

NOT

NOT

NOT

0

0

BS

BS

B3H

R/W

TXT19

TEN

TC

TC

TC

0

0

TS

TS

B4H

R/W

TXT20

DRCS ENABLE

OSD PLANES

EXTENDED SPECIAL GRAPHICS

CHAR SELECT ENABLE

OSD LANG ENABLE

OSD LAN

OSD LAN

OSD LAN

B5H

R/W

TXT21

DISP LINE

DISP LINES

CHAR SIZE

CHAR SIZE

Reserved (0)

CC ON

I2C PORT EN

CC/TXT

B6H

R

TXT22

GPF

GPF

GPF

GPF

GPF

GPF

GPF

GPF

B7H

R/W

CCLIN

0

0

0

CS

CS

CS

CS

CS

B8H

R/W

IP

0

PES2

PCC

PDET

PT1

PX1

PT0

PX0

B9H

R/W

TXT17

0

FORCE ACQ

FORCE ACQ

FORCE DISP

FORCE DISP

SCREEN COL

SCREEN COL

SCREEN COL

BAH

R

WSS1

0

0

0

WSS ERROR

WSS

WSS

WSS

WSS

BBH

R

WSS2

0

0

0

WSS ERROR

WSS

WSS

WSS

WSS

2003 Nov 11

31

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ADD

R/W

Names

UOCIII series

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

WSS ERROR

WSS

WSS

WSS

WSS ERROR

WSS

WSS

WSS

BCH

R

WSS3

BDH

R

ADJUST_E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

BEH

R/W

P3CFGA

Reserved

Reserved

Reserved

Reserved

P3CFGA

P3CFGA

P3CFGA

P3CFGA

BFH

R/W

P3CFGB

Reserved

Reserved

Reserved

Reserved

P3CFGB

P3CFGB

P3CFGB

P3CFGB

C0H

R/W

TXT0

X24 POSN

DISPLAY X24

AUTO FRAME

DISABLE HEADER ROLL

DISPLAY STATUS ROW ONLY

DISABLE FRAME

VPS ON

INV ON

C1H

R/W

TXT1

EXT PKT OFF

8 BIT

ACQ OFF

X26 OFF

Reserved

FIELD POLARITY

H POLARITY

V POLARITY

C2H

R/W

TXT2

ACQ BANK

REQ

REQ

REQ

REQ

SC

SC

SC

C3H

R/W

TXT3

ACQ BANK

ACQ BANK

ACQ BANK

PRD

PRD

PRD

PRD

PRD

C4H

R/W

TXT4

OSD BANK ENABLE

QUAD WIDTH ENABLE

EAST/WEST

DISABLE DOUBLE HEIGHT

0

0

TRANS ENABLE

SHADOW ENABLE

C5H

R/W

TXT5

BKGND OUT

BKGND IN

CORB OUT

CORB IN

TEXT OUT

TEXT IN

PICTURE ON OUT

PICTURE ON IN

C6H

R/W

TXT6

BKGND OUT

BKGND IN

CORB OUT

CORB IN

TEXT OUT

TEXT IN

PICTURE ON OUT

PICTURE ON IN

C7H

R/W

TXT7

STATUS ROW TOP

CURSOR ON

REVEAL

BOTTOM/TOP

DOUBLE HEIGHT

BOX ON 24

BOX ON 1-23

BOX ON 0

C8H

R/W

TXT8

(Reserved) 0

FLICKER STOP ON

HUNT

DISABLE SPANISH

PKT 26 RECEIVED

WSS RECEIVED

WSS ON

(Reserved) 0

C9H

R/W

TXT9

CURSOR FREEZE

CLEAR MEMORY

A0

R

R

R

R

R

CAH

R/W

TXT10

CHAR 16/12

-

C

C

C

C

C

C

CBH

R/W

TXT11

D

D

D

D

D

D

D

D

CCH

R

TXT12

525/625 SYNC

ROM VER

ROM VER

ROM VER

ROM VER

ROM VER

1

VIDEO SIGNAL QUALITY

CDH

R/W

TXT14

DISPLAY BANK

DISPLAY BANK

DISPLAY BANK

DISPLAY BANK

PAGE

PAGE

PAGE

PAGE

CEH

R/W

TXT15

MICRO BANK

MICRO BANK

MICRO BANK

MICRO BANK

BLOCK

BLOCK

BLOCK

BLOCK

CFH

R

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E31>

ADJUST E3

D0H

R/W

C

AC

F0

RS1

RS0

OV

-

P

D1H

R

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

D2H

R/W

TDACL

TD

TD

TD

TD

TD

TD

TD

TD

D3H

R/W

TDACH

TPWE

0

TD

TD

TD

TD

TD

TD

D4H

R/W

P3DCXOCTR L

P3DCXOMUX

P3DCXOCAP S

P3DCXOCAP S

P3DCXOCAPS

P3DCXOCAPS

P3DCXOCAP S

P3DCXOCAPS

P3DCXOCAPS

D5H

R/W

PWM0

PW0E

Reserved (0)

PW0V

PW0V

PW0V

PW0V

PW0V

PW0V

D6H

R/W

PWM1

PW1E

0

PW1V

PW1V

PW1V

PW1V

PW1V

PW1V

2003 Nov 11

ADJUST_E3

PSW ADJUST_E4

32

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ADD

R/W

Names CCDAT1

UOCIII series

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

CCD1

CCD1

CCD1

CCD1

CCD1

CCD1

CCD1

CCD1

D7H

R

D8H

R/W

S1CON

EN_I2CINT

ENSI

STA

STO

SI

AA

0

0

D9H

R

S1STA

STAT

STAT

STAT

STAT

STAT

0

0

0

DAH

R/W

S1DAT

DAT

DAT

DAT

DAT

DAT

DAT

DAT

DAT

DBH

R/W

S1ADR

ADR

ADR

ADR

ADR

ADR

ADR

ADR

GC

DCH

R/W

PWM3

PW3E

0

PW3V

PW3V

PW3V

PW3V

PW3V

PW3V

DDH

R/W

PWM4

PW4E

0

PW4V

PW4V

PW4V

PW4V

PW4V

PW4V

DEH

R/W

HSBIR

0

0

0

HSB

HSB

HSB

HSB

HSB

DFH

R/W

FSBIR

F/S

FSB

FSB

FSB

FSB

FSB

FSB

FSB

E0H

R/W

ACC

ACC

ACC

ACC

ACC

ACC

ACC

ACC

ACC

E1H

R/W

TXT29

TEN B

TS B

TS B

OSD PLANES B

OSD LANG ENABLE B

OSD LAN B

OSD LAN B

OSD LAN B

E2H

R/W

TXT30

TC B

TC B

TC B

BOTTOM/TOP B

DOUBLE HEIGHT B

STATUS ROW TOP B

DISPLAY X24 B

DISPLAY STATUS ROW ONLY B

E3H

R/W

RDS_F0_F1

F0

F0

F0

F0

F1

F1

F1

F1

E4H

R/W

PWM2

PW2E

0

PW2V

PW2V

PW2V

PW2V

PW2V

PW2V

COEF

COEF

COEF

COEF

COEF

COEF

COEF

E5H

R/W

RDS_COEF_ H

COEF

E6H

R/W

RDS_COEF_ L

COEF

COEF

COEF

COEF

COEF

COEF

COEF

COEF

E7H

R

CCDAT2

CCD2

CCD2

CCD2

CCD2

CCD2

CCD2

CCD2

CCD2

E8H

R/W

SAD

VHI

CH

CH

ST

SAD

SAD

SAD

SAD

SYNC

DOFL

RSTD

LBIN

LBIN

LBIN

ELB

ELB

E9H

R

RDS_STAT

EAH

R

RDS_LDATH

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

EBH

R

RDS_LDATL

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

ECH

R

RDS_PDATH

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

EDH

R

RDS_PDATL

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

EFH

R/W

RCP6

RCP ON

NFP

NGP

0

0

RCPSET

RCPSET

RCPSET

F0H

R/W

B

B

B

B

B

B

B

B

B

BBC

BBC

BBC

BBC

BBC

EPB

EPB

F1H

R

RDS_CNT1

BBC

F2H

R

RDS_CNT2

GBC

GBC

GBC

GBC

GBC

PBIN

PBIN

PBIN

F3H

R/W

RDS_CTRL1

-

RBDS

MBBL

MBBL

MBBL

MBBL

MBBL

MBBL

F4H

R/W

RDS_CTRL2

SYM

SYM

MGBL

MGBL

MGBL

MGBL

MGBL

MGBL

F5H

R/W

RDS_CTRL3

DAC

DAC

NWSY

MBBG

MBBG

MBBG

MBBG

MBBG

F6H

R/W

I2S

I2S_CLK

I2S_CLK

EN_I2S_DI1

EN_I2SDO1

EN_I2SDO2

EN_I2SCLK

EN_I2SWS

rds_clkin

F7H

R

TXT35

9FF

9FF

9FF

9FF

GPF

GPF

GPF

GPF

F8H

R/W

TXT13

VPS RECEIVED

PAGE CLEARING

525 DISPLAY

525 TEXT

625 TEXT

PKT 8/30

FASTEXT

0

2003 Nov 11

33

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ADD

R/W

Names

UOCIII series

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

SCAVEM_EN

0

0

PULSE_ WIDTH

PULSE_ WIDTH

EARLY

EARLY

EARLY

F9H

R/W

SCAVTXT

FAH

R/W

XRAMP

XRAMP

XRAMP

XRAMP

XRAMP

XRAMP

XRAMP

XRAMP

XRAMP

FBH

R/W

ROMBK

STANDBY

SW_RST

TEMP_140

TEMP_130

0

ROMBK

ROMBK

ROMBK

FCH

R

TXT36

-

-

-

BFF

BFF

BFF

BFF

BFF

FDH

R

TEST

TEST

TEST

TEST

TEST

TEST

TEST

TEST

TEST

FEH

W

WDTKEY

WKEY

WKEY

WKEY

WKEY

WKEY

WKEY

WKEY

WKEY

FFH

R/W

WDV

WDV

WDV

WDV

WDV

WDV

WDV

WDV

Table 5

WDT

SFR Map

A description of each the SFR bits is shown in Table 6. The SFRs are in alphabetical order. Table 6

SFR Bit description

Names ACC

Add

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

E0H

ACC

ACC

ACC

ACC

ACC

ACC

ACC

ACC

00H

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

ADJUST E0

XXH

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

ADJUST E1

XXH

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

ADJUST E2

XXH

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E3

ADJUST E3

XXH

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

ADJUST E4

XXH

P3DCXOCAP S

P3DCXOCAP S

P3DCXOCAPS

P3DCXOCAP S

P3DCXOCAP S

P3DCXOCAP S

XXH

ACC ADJUST_E0

AEH

ADJUST E0 ADJUST_E1

AFH

ADJUST E1 ADJUST_E2

BDH

ADJUST E2 ADJUST_E3

CFH

ADJUST E3 ADJUST_E4

D1H

ADJUST E4 P3DCXOCTRL

D4H

P3DCXOMUX

P3DCXOCAPS B

CCDAT1

2003 Nov 11

Accumulator value ADJUST E0

For internal testing purpose. ADJUST E1

ADJUST E1

For internal testing purpose. ADJUST E2

ADJUST E2

For internal testing purpose. ADJUST E3

ADJUST E3

For internal testing purpose. ADJUST E4

ADJUST E4

For internal testing purpose. P3DCXOMUX

P3DCXOCAP S

DCXO Cap. Bank Selection:0 - P3DCXOCAPS 1 - SSD Nicam

DCXO Cap. Bank tuning for NICAM.

F0H

B

B

B Register value

D7H

CCD1

B

B

B

B

B

B

B

00H

CCD1

CCD1

CCD1

CCD1

CCD1

CCD1

CCD1

00H

34

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add CCD1

CCDAT2

E7H CCD2

CCLIN

B7H CS

DPH

83H DPH

DPL

82H DPL

FSBIR

DFH F/S

FSB HSBIR

DEH HSBIR

I2S

F6H

I2S_CLK

EN_I2SDI1

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

CCD2

CCD2

CCD2

CCD2

CCD2

CCD2

00H

0

CS

CS

CS

CS

CS

15H

DPH

DPH

DPH

DPH

DPH

DPH

00H

DPL

DPL

DPL

DPL

00H

FSB

FSB

FSB

FSB

00H

Closed Caption first data byte CCD2

CCD2

Closed Caption second data byte 0

0

Closed caption Slice line using 525 line number. DPH

DPH

Data Pointer High byte, used with DPL to address auxiliary memory DPL

DPL

DPL

F/S

FSB

FSB

Determine the SCLH-out frequency in F/S-mode 0

0

0

HSB

HSB

HSB

HSB

HSB

00H

EN_I2SDI1

EN_I2SDO1

EN_I2SDO2

EN_I2SCLK

EN_I2SWS

rds_clkin

00H

EDET

ET1

EX1

ET0

EX0

00H

Determine the SCLH-out frequency in Hs-mode I2S_CLK

I2S_CLK

I2S Clock Output Selection:00 - 256fs 01 - 128fs 10 - 64fs 11 - invalid fs = 32kHz Enable I2S Data Input 1 alternative function to port pin:0 - GPIO function 1 - I2S Data Input 1

EN_I2SDO2

Enable I2S Data Output 2 alternative function to port pin:0 - GPIO function 1 - I2S Data Output 2

EN_I2SCLK

Enable I2S Clock Output alternative function to port pin:0 - GPIO function 1 - I2S Clock Output

EN_I2SWS

Enable I2S Word Select alternative function to port pin:0 - GPIO function 1 - I2S Word Select

A8H EA

EA

ES2

ECC

Disable all interrupts (0), or use individual interrupt enable bits (1) Enable I2C interrupt.

ECC

Enable Closed Caption interrupt

ET1

2003 Nov 11

For RDS debugging / evaluation only.

ES2

EDET

FSB

0 - the duty cycle of SCLH-out is according the Standard mode requirement. 1 - the duty cycle of SCLH-out is according the Fast mode requirement.

Enable I2S Data Output 1 alternative function to port pin:0 - GPIO function 1 - I2S Data Output 1

IE

DPL

Data pointer low byte, used with DPH to address auxiliary memory

EN_I2SDO1

rds_clkin

UOCIII series

Enable Supply Dip Monitor Interrupt. Enable Timer 1 interrupt

35

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

IEN1

BIT7

BIT6

EX1

Enable External interrupt 1

ET0

Enable Timer 0 interrupt

EX0

Enable External interrupt 0

84H EX2 ERDS

-

Enable Timer 2 interrupt

EBUSY

Enable BUSY interrupt

PCC PDET

IP1

P1

Priority Timer 0 interrupt

PX0

Priority External Interrupt 0

P3

PBUSY

Priority BUSY Interrupt

B0H P3

ERDS

EUART

ET2PR

EBUSY

00H

PCC

PDET

PT1

PX1

PT0

PX0

00H

-

PX2

PRDS

PUART

PT2PR

PBUSY

00H

P0

P0

P0

P0

P0

P0

00H

P1

P1

P1

P1

P1

P1

C3H

P2

P2

P2

P2

P2

P2

00H

Reserved

Reserved

P3

P3

P3

P3

C0H

Priority RDS/RBDS Interrupt.

Priority Timer 2 interrupt

P2

EX2

Priority External Interrupt 2.

PT2PR

A0H

-

-

Priority UART Interrupt.

P1 P2

-

PUART

90H

RESET

Priority Supply Dip Monitor Interrupt.

PT0

P0

BIT0

Priority Closed Caption Interrupt

Priority External Interrupt 1

80H

BIT1

Priority I2C interrupt

PX1

PRDS

BIT2

PES2

Priority Timer 1 interrupt

PX2

P0

0

PT1

85H

BIT3

Enable RDS/RBDS Interrupt.

ET2PR

PES2

BIT4

Enable External Interrupt 2.

Enable UART Interrupt.

B8H

BIT5

-

EUART

IP

UOCIII series

Reserved

Reserved

Port 0 I/O register connected to external pins P1

P1

Port 1 I/O register connected to external pins Reserved

Reserved

Port 2 I/O register connected to external pins Reserved

Reserved

Port 3 I/O register connected to external pins

P0CFGA

96H

Reserved

Reserved

P0CFGA

P0CFGA

P0CFGA

P0CFGA

P0CFGA

P0CFGA

00H

P0CFGB

97H

Reserved

Reserved

P0CFGB

P0CFGB

P0CFGB

P0CFGB

P0CFGB

P0CFGB

00H

P0CFGB/P0CFGA = 00

MODE 0 Open Drain

P0CFGB/P0CFGA = 01

MODE 1 Quasi Bi-Directional

P0CFGB/P0CFGA = 10

MODE2 High Impedance

2003 Nov 11

36

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

BIT7

P0CFGB/P0CFGA = 11

BIT6

UOCIII series

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

MODE3 Push Pull

P1CFGA

9EH

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

P1CFGA

00H

P1CFGB

9FH

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

P1CFGB

00H

P1CFGB/P1CFGA = 00

MODE 0 Open Drain

P1CFGB/P1CFGA = 01

MODE 1 Quasi Bi-Directional

P1CFGB/P1CFGA = 10

MODE2 High Impedance

P1CFGB/P1CFGA = 11

MODE3 Push Pull

P2CFGA

A6H

Reserved

Reserved

P2CFGA

P2CFGA

P2CFGA

P2CFGA

P2CFGA

P2CFGA

00H

P2CFGB

A7H

Reserved

Reserved

P2CFGB

P2CFGB

P2CFGB

P2CFGB

P2CFGB

P2CFGB

00H

P2CFGB/P2CFGA = 00

MODE 0 Open Drain

P2CFGB/P2CFGA = 01

MODE 1 Quasi Bi-Directional

P2CFGB/P2CFGA = 10

MODE2 High Impedance

P2CFGB/P2CFGA = 11

MODE3 Push Pull

P3CFGA

BEH

Reserved

Reserved

Reserved

Reserved

P3CFGA

P3CFGA

P3CFGA

P3CFGA

00H

P3CFGB

BFH

Reserved

Reserved

Reserved

Reserved

P3CFGB

P3CFGB

P3CFGB

P3CFGB

00H

WLE

GF1

GF0

PD

IDL

00H

RS

OV

-

P

00H

P3CFGB/P3CFGA = 00

MODE 0 Open Drain

P3CFGB/P3CFGA = 01

MODE 1 Quasi Bi-directional

P3CFGB/P3CFGA = 10

MODE2 High Impedance

P3CFGB/P3CFGA = 11

MODE3 Push Pull

PCON

87H

SMOD

SMOD ARD

RFI

WLE

PSW

Disable ALE during internal access to reduce Radio Frequency Interference ’0’: Enable ’1’: Disable Watch Dog Timer enable ’0’: Disable ’1’: Enable

GF0

General purpose flag

D0H

Power-down activation bit Idle mode activation bit C

C

2003 Nov 11

Auxiliary RAM Disable, All MOVX instructions access the off-chip data memory. ‘0’: Enable ‘1’: Disable In application mode, this bit should keep ‘0’.

General purpose flag

IDL

RFI

UART Baud Rate Double Control

GF1

PD

ARD

AC

F0

RS

Carry Bit

AC

Auxiliary Carry bit

F0

Flag 0, General purpose flag

37

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add RS

OV P PWM0

D5H PW0E

PW0V PWM1

D6H PW1E

PW1V PWM2

E4H PW2E

PW2V PWM3

DCH PW3E

PW3V PWM4

DDH PW4E

PW4V RCP1

86H DAT

RCP2

95H DAT

RCP3

8EH RA

RCP4

8FH

BIT7

BIT6

PW0E

Reserved (0)

2003 Nov 11

EFH

BIT2

BIT1

BIT0

RESET

PW0V

PW0V

PW0V

PW0V

PW0V

PW0V

00H

PW1V

PW1V

PW1V

PW1V

PW1V

PW1V

00H

PW2V

PW2V

PW2V

PW2V

PW2V

PW2V

00H

PW3V

PW3V

PW3V

PW3V

PW3V

PW3V

00H

PW4V

PW4V

PW4V

PW4V

PW4V

PW4V

00H

DAT

DAT

DAT

DAT

DAT

DAT

00H

DAT

DAT

X0H

0 - Disable Pulse Width Modulator 0 1 - Enable Pulse Width Modulator 0 Pulse Width Modulator high time PW1E

0

0 - Disable Pulse Width Modulator 1 1 - Enable Pulse Width Modulator 1 Pulse Width Modulator high time PW2E

0

0 - Disable Pulse Width Modulator 2 1 - Enable Pulse Width Modulator 2 Pulse Width Modulator high time PW3E

0

0 - Disable Pulse Width Modulator 3 1 - Enable Pulse Width Modulator 3 Pulse Width Modulator high time PW4E

0

0 - Disable Pulse Width Modulator 4 1 - Enable Pulse Width Modulator 4 Pulse Width Modulator high time DAT

DAT

Data location shared by CDIV, AL, AH, BL, BH Reset value of CDIV, AL, and BL are 00H; reset value of AH and BH are FFH. -

-

-

-

DAT

DAT

Data location shared by CDIV, AL, AH, BL and BH Reset value of CDIV, AL, and BL are 0H; reset value of AH and BH are FH. RA

RA

RA

RA

RA

RA

RA

RA

00H

RB

RB

RA

RA

RA

RA

00H

RB

RB

RB

RB

RB

RB

00H

NGP

0

0

RCPSET

RCPSET

RCPSET

00H

LOW time Result (bit 7:0) minus AL RB

RB

LOW time Result (bit 11:8)

RCP6

BIT3

Parity bit

RA

RB

BIT4

Overflow flag

High time Result (bit 11:8)

9BH

BIT5

Register Bank selector bits RS = 00, Bank0 (00H - 07H) RS = 01, Bank1 (08H - 0FH) RS = 10, Bank2 (10H - 17H) RS = 11, Bank3 (18H - 1FH)

RB

RCP5

UOCIII series

RB

RB

High time Result (bit 7:0) minus BL RCP ON

NFP

38

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add RCP ON

0 - First Pulse 1 - Not First Pulse

NGP

0 - Good Pulse 1 - Not Good Pulse

E9H

RDS_LDATH

DOFL

Data overflow flag

RSTD

Reset detected

EAH

LDAT RDS_LDATL

EBH LDAT

RDS_PDATH

ECH PDAT

RDS_PDATL

EDH PDAT

RDS_CNT1

F1H BBC EPB

RDS_CNT2

F2H GBC

2003 Nov 11

SYNC Synchronization found

ELB

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

LBIN

LBIN

LBIN

ELB

ELB

1CH

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

00H

LDAT

LDAT

LDAT

LDAT

LDAT

LDAT

00H

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

00H

PDAT

PDAT

PDAT

PDAT

PDAT

PDAT

00H

BBC

BBC

BBC

BBC

EPB

EPB

00H

GBC

GBC

PBIN

PBIN

PBIN

07H

Define DAT value:000 - CDIV is accessed via DAT, default = 000H 001 - AL is accessed via DAT, default = 000H 010 - AH is accessed via DAT, default = FFFH 011 - BL is accessed via DAT, default = 000H 100 - BH is accessed via DAT, default = FFFH 101 - SPF is accessed via DAT, default = 003H

SYNC

LBIN

BIT6

0 - Remote Control Pre-processor disable 1 - Remote Control Pre-processor enable

NFP

RCPSET

RDS_STAT

BIT7

UOCIII series

DOFL

RSTD

Last block identification LBIN=000, block A LBIN=001, block B LBIN=010, block C LBIN=011, block D LBIN=100, block C’ LBIN=101, block E (RBDS mode) LBIN=110, invalid block E (RDS mode) LBIN=111, invalid block Error status last block ELB=00, no errors detect ELB=01, max. 2 bits ELB=10, max. 5 bits ELB=11, uncorrectable block LDAT

LDAT

Last processed block data high byte LDAT

LDAT

Last processed block data low byte PDAT

PDAT

Previous processed block data high byte PDAT

PDAT

Previous processed block data low byte BBC

BBC

Bad Blocks Counter Error Status Previous Block EPB=00 - no errors detected EPB=01 - burst error of maximum 2 bits corrected EPB=10 - burst error of maximum 5 bits corrected EPB=11 - uncorrectable block GBC

GBC

GBC

Good Blocks Counter (Only 5 MSBs are available)

39

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add PBIN

RDS_CTRL1

F3H RBDS

MBBL RDS_CTRL2

F4H SYM

MGBL RDS_CTRL3

F5H DAC

NWSY MBBG RDS_F0_F1

E3H

BIT7

BIT6

-

E6H

COEF ROMBK

FBH

BIT0

RESET

MBBL

MBBL

MBBL

MBBL

20H

SYM

MGBL

MGBL

MGBL

MGBL

MGBL

MGBL

20H

Allow RBDS ‘E’ Block ‘0’ - RDS mode ‘1’ - RBDS mode Max Bad Block Lose SYM

Synchronization Mode SYM=00 - no error correction SYM=01 - error correction of a burst error maximum 2 bits SYM=10 - error correction of a burst error maximum 5 bits SYM=11 - no error correction Max Good Block Lose DAC

DAC

NWSY

MBBG

MBBG

MBBG

MBBG

MBBG

00H

F0

F0

F1

F1

F1

F1

32H

COEF

COEF

COEF

COEF

COEF

COEF

4BH

COEF

COEF

COEF

COEF

COEF

COEF

CAH

TEMP_140

TEMP_130

0

ROMBK

ROMBK

ROMBK

00H

Data output control DAC=00, standard mode DAC=01, fast PI search mode DAC=10, reduced data request DAC=11, decoder bypass Start new synchronization Max bad blocks gain F0

F0

COEF

COEF

DCS Coefficient High Byte COEF

COEF

DCS Coefficient Low Byte STANDBY

SW_RST

STANDBY

0 - Disable Stand-by Mode 1 - Enable Stand-by Mode

SW_RST

0 - Disable Software Reset 1 - Enable Software Reset

TEMP_140

0 - Temperature of the device below 140C 1 - Temperature of the device above 140C

TEMP_130

0 - Temperature of the device below 130C 1 - Temperature of the device above 130C

2003 Nov 11

BIT1

MBBL

Coarse Division Factor F1

COEF

BIT2

MBBL

F1

RDS_COEF_L

BIT3

RBDS

Coarse Division Factor F0

E5H

BIT4

Previous Block Identification PBIN=000 - block A PBIN=001 - block B PBIN=010 - block C PBIN=011 - block D PBIN=100 - block C’ PBIN=101 - block E (RBDS mode) PBIN=110 - invalid block E (RDS mode) PBIN=111 - invalid block

F0

RDS_COEF_H

BIT5

UOCIII series

40

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

ROMBK

S0BUF

9AH S0BUF

S0CON

99H SM

SM

S1ADR

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

S0BUF

00H

SM

SM

REN

TB8

RB8

TI

RI

00H

ROM Bank selection ROMBK = 000, Bank0 ROMBK = 001, Bank1 ROMBK = 010, Bank2 ROMBK = 011, Bank3 ROMBK = 100, Bank4 ROMBK = 101, Bank5 ROMBK = 110, Bank6 ROMBK = 111, Reserved S0BUF UART data buffer SM

UART Mode selection bits SM = 00, Shift Register SM = 01, 8-bit UART (variable baud rate) SM = 10, 9-bit UART SM = 11, 9-bit UART (variable baud rate) Enables the multi processor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if the received 9th data bit is ’0’. In mode 1, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if no valid stop bit was received. In mode 0, SM2 has no influence. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception.

TB8

Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired.

RB8

In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 is ’0’, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Loading of RB8 in modes 1, 2 and 3 depends on SM2.

TI

Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.

RI

Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.

ADR GC

D8H EN_I2CINT

ENSI

ADR

ADR

ADR

ADR

ADR

ADR

ADR

GC

00H

STA

STO

SI

AA

0

0

00H

I2C Slave Address 0 - Disable I2C general call address 1 - Enable I2C general call address EN_I2CINT

ENSI

Setting by software 0- the I2C interrupt signal is always non-active 1- the I2C interrupt signal is activated when if the SI is set 0 - Disable I2C interface 1 - Enable I2C interface

STA

START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition.

STO

STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware

SI

2003 Nov 11

BIT6

REN

DBH

S1CON

BIT7

UOCIII series

Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: -A START condition is generated in master mode. -The own slave address has been received during AA=1 -The general call address has been received while S1ADR.GC and AA=1 -A data byte has been received or transmitted in master mode (even if arbitration is lost) -A data byte has been received or transmitted as selected slave A STOP or START condition is received as selected slave receiver or transmitter While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.

41

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add AA

S1DAT

BIT7

S1STA

D9H STAT

SAD

E8H VHI

CH

ST

SAD SADB

98H SSD_ON

DC_COMP

SAD SCAVTXT

F9H

SCAVEM_EN

PULSE_WIDTH

EARLY

SP

81H SP

TCON

2003 Nov 11

88H

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions -Own slave address is received. -General call address is received(S1ADR.GC=1) -A data byte is received, while the device is programmed to be a master receiver -A data byte is received, while the device is selected slave receiver When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.

DAH DAT

BIT6

UOCIII series

DAT I2C

DAT

DAT

DAT

DAT

DAT

DAT

DAT

00H

STAT

STAT

STAT

STAT

0

0

0

F8H

CH

CH

ST

SAD

SAD

SAD

SAD

00H

Data

STAT I2C Interface Status VHI

0 - Analogue input voltage less than or equal to DAC voltage 1 - Analogue input voltage greater then DAC voltage ADC Input channel select CH = 00,ADC3 CH = 01,ADC0 CH = 10,ADC1 CH = 11,ADC2 Initiate voltage comparison between ADC input Channel and SAD value Note: Set by Software and reset by Hardware Most Significant nibble of DAC input word SSD_ON

-

-

DC_COMP

SAD

SAD

SAD

SAD

80H

0

PULSE_ WIDTH

PULSE_ WIDTH

EARLY

EARLY

EARLY

00H

0 - Disable SSD Function 1 - Enable SSD Function 0 - Disable DC Comparator mode 1 - Enable DC Comparator mode Least Significant nibble of 8 bit SAD value SCAVEM_ EN

0

0 - Disable scavem text output for R, G, and B signals 1 - Enable scavem text output for R, G, and B signals SCAVEM Text signal pulse width PULSE_WIDTH=00, 37ns PULSE_WIDTH=01, 74ns PULSE_WIDTH=10, 111ns PULSE_WIDTH=11, 148ns SCAVEM Text output to Video Signal Processor earlier than R,G, and B signals EARLY=000, 0 ns EARLY=001, 74 ns EARLY=010, 111 ns EARLY=011, 148 ns EARLY=100, 185 ns EARLY=101, 212 ns EARLY=110, 259 ns EARLY=111, 296 ns SP

SP

SP

SP

SP

SP

SP

SP

07H

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

Stack Pointer TF1

TF1

Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine

TR1

Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off

TF0

Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine

42

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add TR0

TDACH

BIT7

BIT6

BIT5

Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.

IE0

Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.

IT0

Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts TPWE

0

D2H TD 8CH TH0 8DH TH1 8AH TL0 8BH TL1

TMOD

89H

TD

TD

TD

TD

TD

00H

TD

TD

TD

TD

TD

TD

00H

TH0

TH0

TH0

TH0

TH0

TH0

TH0

00H

TH1

TH1

TH1

TH1

TH1

TH1

TH1

00H

TL0

TL0

TL0

TL0

TL0

TL0

TL0

00H

TL1

TL1

TL1

TL1

TL1

TL1

TL1

00H

TD

TD

Tuning Pulse Width Modulator Low Byte TH0 Timer 0 high byte TH1 Timer 1 high byte TL0 Timer 0 low byte TL1 Timer 1 low byte GATE

C/T

M1

M0

GATE

Timer / Counter 1 GATE C/T M1,M0

GATE C/T M1,M0

TP2CL

9CH TP2CL

TP2CH

9DH TP2CH

2003 Nov 11

RESET

TD

Tuning Pulse Width Modulator High Byte

TL1

BIT0

IT1

TD

TL0

BIT1

Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.

0 - Disable Tuning Pulse Width Modulator 1 - Enable Tuning Pulse Width Modulator

TH1

BIT2

Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off

TPWE

TH0

BIT3

IE1

D3H

TDACL

BIT4

UOCIII series

C/T

M1

M0

00H

Timer / Counter 0

Gating Control Timer /Counter 1 Counter/Timer 1 selector Mode control bits Timer/Counter 1 M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler M1,M0 = 01, 16 bit time interval or event counter M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1 M1,M0 = 11, stopped Gating control Timer/Counter 0 Counter/Timer 0 selector Mode Control bits Timer/Counter 0 M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler M1,M0 = 01, 16 bit time interval or event counter M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0 M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

TP2CL

00H

TP2CH

TP2CH

TP2CH

TP2CH

TP2CH

00H

Indicate the low byte of the Time 2 current value. TP2CH

TP2CH

TP2CH

Indicate the high byte of the Time 2 current value.

43

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

TP2H

92H TP2H

TP2L

91H TP2L

TP2PR

93H TP2PR

TP2CRL

94H

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

TP2H

00H

TP2L

TP2L

TP2L

TP2L

TP2L

00H

TP2PR

TP2PR

TP2PR

TP2PR

TP2PR

00H

Timer 2 high byte, never change unless updated by the software. TP2L

TP2PR

Timer 2 Status. 0 - No Overflow. 1 - Overflow.

TXT0

C0H

X24 POSN

DISLAY X24

AUTO FRAME

DISABLE HEADER ROLL

TP2PR

-

TP2CRL

TEST

-

-

-

-

TP2CRL

TP2CRL

00H

TEST

TEST

TEST

TEST

TEST

TEST

TEST

A0H

DISPLAY X24

AUTO FRAME

DISABLE HEADER ROLL

DISPLAY STATUS ROW ONLY

DISABLE FRAME

VPS ON

INV ON

00H

full-field

FIELD POLARITY

H POLARITY

V POLARITY

00H

TEST For internal testing use. X24 POSN

0 - Store X/24 in extension memory 1 - Store X/24 in basic page memory with packets 0 to 23 0 - Display row 24 from basic page memory 1 - Display row 24 from appropriate location in extension memory 0 - Normal Frame output 1 - Frame output is switched off automatically if any video displayed 0 - Write rolling headers and time to current display page 1 - Disable writing of rolling headers and time to into memory 0 - Display normal page rows 0 to 24 1- Display only row 24

DISABLE FRAME

0 - Normal Frame output 1 - Force Frame output to be low (0)

VPS ON

0 - VPS acquisition off 1 - VPS acquisition on

INV ON

0 - Inventory page off 1 - Inventory page on

C1H

EXT PKT OFF

8 BIT

ACQ OFF

X26 OFF

full-field

2003 Nov 11

TP2PR

-

DISPLAY STATUS ROW ONLY

TXT1

TP2L

Timer 2 Pre-scaler, never change unless updated by the software

Timer 2 Control. 0 - Timer 2 disabled. 1 - Timer 2 enabled.

FDH

TP2L

Timer 2 low byte, never change unless updated by the software.

TP2CRL

TEST

UOCIII series

EXT PKT OFF

8 BIT

ACQ OFF

X26 OFF

0 - Acquire extension packets X/24,X/27,8/30/X 1 - Disable acquisition of extension packets 0 - Error check and/or correct packets 0 to 24 1 - Disable checking of packets 0 to 24 written into memory 0 - Write requested data into display memory 1 - Disable writing of data into Display memory 0 - Enable automatic processing of X/26 data 1 - Disable automatic processing of X/26 data unused, must keep reset value -> ‘0’

44

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

FIELD POLARIY

BIT7

BIT6

BIT5

0 - Hsync reference edge is positive going 1 - Hsync reference edge is negative going

V POLARITY

0 - Vsync reference edge is positive going 1 - Vsync reference edge is negative going

C2H

ACQ_BANK REQ SC TXT3

C3H

ACQ_BANK

PRD TXT4

C4H

OSD BANK ENABLE

QUAD WIDTH ENABLE

EAST/WEST

DISABLE DOUBLE HEIGHT TRANS ENABLE

SHADOW ENABLE

TXT5

C5H

BKGND OUT

BKGND IN

2003 Nov 11

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

REQ

REQ

REQ

SC

SC

SC

00H

ACQ BANK

PRD

PRD

PRD

PRD

PRD

00H

DISABLE DBL HEIGHT

0

0

TRANS ENABLE

SHADOW ENABLE

00H

TEXT OUT

TEXT IN

PICTURE ON OUT

PICTURE ON IN

03H

0 - Vsync pulse in first half of line during even field 1 - Vsync pulse in second half of line during even field For MCM package, this bit should be set to ‘1’

H POLARITY

TXT2

UOCIII series

ACQ BANK

REQ

Should combine TXT3 ACQ_BANK Page request Start column of page request ACQ BANK

ACQ BANK

Combine with TXT2 ACQ_BANK 0000 - Select BLOCK 0 ~ 9 for acquisition storage 0001 - Reserved 0010 - Reserved 0011 - Reserved 0100 - Reserved 0101 - Reserved 0110 - Reserved 0111 - Reserved 1000 - Reserved 1001 - Reserved 1010 - Reserved 1011 - Reserved 1100 - Reserved 1101 - Reserved 1110 - Reserved 1111 - Reserved Page Request data OSD BANK ENABLE

QUAD WIDTH ENABLE

EAST/WEST

0 - Only alpha numeric OSD characters available, 32 locations 1 - Alternate OSD location available via graphic attribute, additional 32 location 0 - Disable display of Quadruple width characters 1 - Enable display of Quadruple width characters 0 - Western language selection of character codes A0 to FF 1 - Eastern character selection of character codes A0 to FF 0 - Allow normal decoding of double height characters 1 - Disable normal decoding of double height characters 0 - Display black background as normal 1 - Display black background as video 0 - Disable display of shadow/fringing 1 - Display shadow/ fringe (default SE black) BKGND OUT

BKGND IN

COR OUT

COR IN

0 - Background colour not displayed outside teletext boxes(teletext page) 1 - Background colour displayed outside teletext boxes(teletext page) 0 - Background colour not displayed inside teletext boxes(teletext page) 1 - Background colour displayed inside teletext boxes(teletext page)

45

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add COR OUT

COR IN

TEXT OUT

TEXT IN

PICTURE ON OUT

PICTURE ON IN

TXT6

C6H

BKGND OUT

BKGND IN

COR OUT

COR IN

TEXT OUT

TEXT IN

PICTURE ON OUT

PICTURE ON IN

TXT7

C7H

STATUS ROW TOP

CURSOR ON

REVEAL

BOTTOM/TOP

DOUBLE HEIGHT

BOX ON 24

BOX ON 1-23

BOX ON 0

2003 Nov 11

BIT7

BIT6

BIT5

UOCIII series

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

COR IN

TEXT OUT

TEXT IN

PICTURE ON OUT

PICTURE ON IN

03H

DOUBLE HEIGHT

BOX ON 24

BOX ON 1-23

BOX ON 0

00H

0 - COR not active outside teletext and OSD boxes(teletext page) 1 - COR active outside teletext and OSD boxes(teletext page) 0 - COR not active inside teletext and OSD boxes(teletext page) 1 - COR active inside teletext and OSD boxes(teletext page) 0 - TEXT not displayed outside teletext boxes(teletext page) 1 - TEXT displayed outside teletext boxes(teletext page) 0 - TEXT not displayed inside teletext boxes(teletext page) 1 - TEXT displayed inside teletext boxes(teletext page) 0 - VIDEO not displayed outside teletext boxes(teletext page) 1 - VIDEO displayed outside teletext boxes(teletext page) 0 - VIDEO not displayed inside teletext boxes(teletext page) 1 - VIDEO displayed inside teletext boxes(teletext page) BKGND OUT

BKGND IN

COR OUT

0 - Background colour not displayed outside teletext boxes(newsflash/subtitle) 1 - Background colour displayed outside teletext boxes(newsflash/subtitle) 0 - Background colour not displayed inside teletext boxes(newsflash/subtitle) 1 - Background colour displayed inside teletext boxes(newsflash/subtitle) 0 - COR not active outside teletext and OSD boxes(newsflash/subtitle) 1 - COR active outside teletext and OSD boxes(newsflash/subtitle) 0 - COR not active inside teletext and OSD boxes(newsflash/subtitle) 1 - COR active inside teletext and OSD boxes(newsflash/subtitle) 0 - TEXT not displayed outside teletext boxes(newsflash/subtitle) 1 - TEXT displayed outside teletext boxes(newsflash/subtitle) 0 - TEXT not displayed inside teletext boxes(newsflash/subtitle) 1 - TEXT displayed inside teletext boxes(newsflash/subtitle) 0 - VIDEO not displayed outside teletext boxes(newsflash/subtitle) 1 - VIDEO displayed outside teletext boxes(newsflash/subtitle) 0 - VIDEO not displayed inside teletext boxes(newsflash/subtitle) 1 - VIDEO displayed inside teletext boxes(newsflash/subtitle) STATUS ROW TOP

CURSOR ON

REVEAL

BOTTOM/ TOP

0 - Display memory row 24 information below teletext page (on display row 24) 1 - Display memory row 24 information above teletext page (on display row 0) 0 - Disable display of cursor 1 - Display cursor at position given by TXT9 and TXT10 0 - Display as spaces characters in area with conceal attribute set 1 - Display characters in area with conceal attribute set 0 - Display memory rows 0 to 11 when double height bit is set 1 - Display memory rows 12 to 23 when double height bit is set 0 - Display each characters with normal height 1 - Display each character as twice normal height. 0 - Disable display of teletext boxes in memory row 24 1 - Enable display of teletext boxes in memory row 24 0 - Disable display of teletext boxes in memory row 1 to 23 1 - Enable display of teletext boxes in memory row 1 to 23 0 - Disable display of teletext boxes in memory row 0 1 - Enable display of teletext boxes in memory row 0

46

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

TXT8

C8H

FLICKER STOP ON

HUNT

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

(Reserved) 0

FLICKER STOP ON

HUNT

DISABLE SPANISH

PKT 26 RECEIVED

WSS RECEIVED

WSS ON

(Reserved) 0

00H

R

R

R

R

R

00H

C

C

C

C

C

00H

D

D

D

D

D

00H

ROM VER

ROM VER

1

VIDEO SIGNAL QUALITY

xxxxxx1xB

0 - Enable ‘Flicker Stopper’ circuitry 1 - Disable ‘Flicker Stopper’ circuitry 0 - Allow automatic hunting for amplitude of data to be acquired 1 - Disable automatic hunting for amplitude

DISABLE SPANISH

0 - Enable special treatment of Spanish packet 26 characters 1 - Disable special treatment of Spanish packet 26 characters

PKT 26 RECEIVED

0 - No packet 26 data has been processed 1 - Packet 26 data has been processed. Note: This flag is set by Hardware and must be reset by Software

WSS RECEIVED

0 - No Wide Screen Signalling data has been processed 1 - Wide Screen signalling data has been processed Note: This flag is set by Hardware and must be reset by Software.

WSS ON

TXT9

C9H

0 - Disable acquisition of WSS data. 1 - Enable acquisition of WSS data. CURSOR FREEZE

CLEAR MEMORY

A0

CURSOR FREEZE

0 - Use current TXT9 and TXT10 values for cursor position. 1 - Lock cursor at current position

CLEAR MEMORY

0 - Clear memory action is finished 1 - Clear memory block pointed to by TXT15 Note: This flag is set by Software and reset by Hardware

A0

R

TXT10

CAH

CHAR A 16/12

C

TXT11

CBH

TXT12

0 - Access memory block pointed to by TXT15 1 - Access extension packet memory Current memory ROW value. Note: Valid range TXT mode 0 to 24, CC mode 0 to 15 CHAR 16/12

CCH

-

C

Character Matrix width on Display Page A and B 0 - 12 pixel width 1 - 16 pixel width Current memory COLUMN value. Note: Valid range TXT mode 0 to 39, CC mode 0 to 47 D

D

D

D

Data value written or read from memory location defined by TXT9, TXT10 and TXT15 625/525 SYNC

ROM VER

ROM VER

ROM VER

625/525 SYNC

0 - 625 line CVBS signal is being received 1 - 525 line CVBS signal is being received

ROM VER

Mask programmable identification for character set ROM Version : 0 - Spanish Flicker Stopper Disabled. 1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6).

ROM VER

General purpose register, bits defined by mask programmable bits

1 VIDEO SIGNAL QUALITY

2003 Nov 11

UOCIII series

Reserved 0 - Acquisition can not be synchronised to CVBS input. 1 - Acquisition can be synchronised to CVBS

47

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

TXT13

F8H

VPS RECEIVED

PAGE CLEARING

525 DISPLAY

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

VPS RECEIVED

PAGE CLEARING

525 DISPLAY

525 TEXT

625 TEXT

PKT 8/30

FASTEXT

0

xxxxxxx0B

DISPLAY BANK

DISPLAY BANK

PAGE

PAGE

PAGE

PAGE

00H

MICRO BANK

MICRO BANK

BLOCK

BLOCK

BLOCK

BLOCK

00H

0 - VPS data not being received 1 - VPS data being received 0 - No page clearing active 1 - Software or Power On page clear in progress 0 - 625 Line synchronisation for Display 1 - 525 Line synchronisation for Display

525 TEXT

0 - 525 Line WST not being received 1 - 525 line WST being received

625 TEXT

0 - 625 Line WST not being received 1 - 625 line WST being received

PKT 8/30

FASTEXT

0 TXT14

CDH

DISPLAY BANK

PAGE TXT15

CEH

MICRO BANK

BLOCK TXT17

2003 Nov 11

B9H

UOCIII series

0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected 1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected 0 - No Packet x/27 data detected 1 - Packet x/27 data detected Reserved DISPLAY BANK

DISPLAY BANK

0000 - Select Page 0 ~ 9 for Display 0001 - Reserved 0010 - Reserved 0011 - Reserved 0100 - Reserved 0101 - Reserved 0110 - Reserved 0111 - Reserved 1000 - Reserved 1001 - Reserved 1010 - Reserved 1011 - Reserved 1100 - Reserved 1101 - Reserved 1110 - Reserved 1111 - Reserved Current Display page MICRO BANK

MICRO BANK

0000 - Select BLOCK 0 ~ 9 for Micro 0001 - Reserved 0010 - Reserved 0011 - Reserved 0100 - Reserved 0101 - Reserved 0110 - Reserved 0111 - Reserved 1000 - Reserved 1001 - Reserved 1010 - Reserved 1011 - Reserved 1100 - Reserved 1101 - Reserved 1110 - Reserved 1111 - Reserved Current Micro block to be accessed by TXT9, TXT10 and TXT11 0

FORCE ACQ

FORCE ACQ

FORCE DISP

FORCE DISP

48

CONFIDENTIAL

SCREEN COL2

SCREEN COL1

SCREEN COL0

00H

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add

BIT7

BIT6

BIT5

FORCE ACQ

00 - Automatic Selection 01 - Force 525 timing, Force 525 Teletext Standard 10 - Force 625 timing, Force 625 Teletext Standard 11 - Force 625 timing, Force 525 Teletext Standard

FORCE DISP

00 - Automatic Selection 01 - Force Display to 525 mode (9 lines per row) 10 - Force Display to 625 mode (10 lines per row) 11 - Not Valid (default to 625)

SCREEN COL

TXT18

B2H NOT

field_indent BS TXT19

B3H TEN

BIT4

NOT

NOT

NOT

NOT

EXTENDED SPECIAL GRAPHICS CHAR SELECT ENABLE

OSD LANG ENABLE OSD LAN TXT21

B5H

TEN

TC

TC

RESET

0

field_indent

BS

BS

00H

TC

0

0

TS

TS

00H

OSD LANG ENABLE

OSD LAN

OSD LAN

OSD LAN

00H

CC ON

I2C PORT EN

CC/TXT

02H

0 - Disable Twist function 1- Enable Twist character set

DRCS ENABLE

OSD PLANES

EXTENDED SPECIAL GRAPHICS

CHAR SELECT ENABLE

0 - Normal OSD characters used 1 - Re-map column 9 to DRCS (TXT and CC modes), 0 - Character code columns 8 and 9 defined as single plane characters 1- Character code columns 8 and 9 defined as double plane characters 0 - Extended Special Graphics disabled (columns 8 & 9 only used for special graphics characters) 1 - Extended Special Graphics enabled (user definable range for special graphics characters) 0 - Disables character set selection in CC display mode 1 - Enables character set selection in CC display mode Enable use of OSD LAN to define language option for display, instead of C12/C13/C14 Alternative C12/C13/C14 bits for use with OSD menus DISP LINES

DISP LINES

CHAR SIZE

DISP LINES

The number of display lines per character row. 00 - 10 lines per character (defaults to 9 lines in 525 mode) 01 - 13 lines per character 10 - 16 lines per character 11 - 18 lines per character

CHAR SIZE

Character matrix size.

CHAR SIZE

Reserved 0)

01 - 13 lines per character (matrix 12x13) 10 - 16 lines per character (matrix 12x16) 11 - 18 lines per character (matrix 16x18)

2003 Nov 11

BIT0

Basic Character set selection

Twist Character set selection

OSD PLANES

BIT1

unused, must keep reset value -> ‘0’

TS

DRCS ENABLE

BIT2

National Option table selection, maximum of 32 when used with East/West bit

Language control bits (C12/C13/C14) that has Twisted character set

B4H

BIT3

Defines colour to be displayed instead of TV picture and black background. The bits are equivalent to the RGB components 000 - Transparent 001 - CLUT entry 9 010 - CLUT entry 10 011- CLUT entry 11 100 - CLUT entry 12 101 - CLUT entry 13 110- CLUT entry 14 111 - CLUT entry 15

TC

TXT20

UOCIII series

49

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add CCON

I2C PORT EN

CC/TXT

TXT22

B6H GPF

TXT23

A9H

NOT B EAST/WEST B

DRCS B ENABLE

BS B TXT24

AAH

BKGND OUT B

BKGND IN B

COR OUT B

COR IN B

TEXT OUT B

TEXT IN B

PICTURE ON OUT B

PICTURE ON IN B TXT25

ABH

BKGND OUT B

BKGND IN B

COR OUT B

COR IN B

TEXT OUT B

2003 Nov 11

BIT7

BIT6

BIT5

UOCIII series

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

0 - Closed Caption acquisition off 1 - Closed Caption acquisition on 0 - Disable I2C PORT EN 1 - Enable I2C PORT EN selection (P1.7/SDA0, P1.6/SCL0) 0 - Display configured for TXT mode 1 - Display configured for CC mode GPF

GPF

GPF

GPF

GPF

GPF

GPF

GPF

XXH

General purpose register, bits defined by mask programmable bits NOT B

NOT B

NOT B

NOT B

EAST/WEST B

DRCS B ENABLE

BS B

BS B

00H

TEXT OUT B

TEXT IN B

PICTURE ON OUT B

PICTURE ON IN B

03H

TEXT OUT B

TEXT IN B

PICTURE ON OUT B

PICTURE ON IN B

03H

National Option table selection for Page B, maximum of 32 when used with East/West bit 0 - Western language selection of character codes A0 to FF on Page B 1 - Eastern language selection of character codes A0 to FF on Page B 0 - Normal OSD characters used on Page B 1 - Re-map column 8/9 to DRCS (TXT and CC modes) on Page B Basic Character set selection for Page B BKGND OUT B

BKGND IN B

COR OUT B

COR IN B

0 - Background colour not displayed outside teletext boxes (Teletext page) 1 - Background colour displayed outside teletext boxes (Teletext page) 0 - Background colour not displayed inside teletext boxes (Teletext page) 1 - Background colour displayed inside teletext boxes (Teletext page) 0 - COR not active outside teletext and OSD boxes (Teletext page) 1 - COR active outside teletext and OSD boxes (Teletext page) 0 - COR not active inside teletext and OSD boxes (Teletext page) 1 - COR active inside teletext and OSD boxes (Teletext page) 0 - TEXT not displayed outside teletext boxes (Teletext page) 1 - TEXT displayed outside teletext boxes (Teletext page) 0 - TEXT not displayed inside teletext boxes (Teletext page) 1 - TEXT displayed inside teletext boxes (Teletext page) 0 - VIDEO not displayed outside teletext boxes (Teletext page) 1 - VIDEO displayed outside teletext boxes (Teletext page) 0 - VIDEO not displayed inside teletext boxes (Teletext page) 1 - VIDEO displayed inside teletext boxes (Teletext page) BKGND OUT B

BKGND IN B

COR OUT B

COR IN B

0 - Background colour not displayed outside teletext boxes (Sub-Title / Newsflash page) 1 - Background colour displayed outside teletext boxes (Sub-Title / Newsflash page) 0 - Background colour not displayed inside teletext boxes (Sub-Title / Newsflash page) 1 - Background colour displayed inside teletext boxes (Sub-Title / Newsflash page) 0 - COR not active outside teletext and OSD boxes (Sub-Title / Newsflash page) 1 - COR active outside teletext and OSD boxes (Sub-Title / Newsflash page) 0 - COR not active inside teletext and OSD boxes (Sub-Title / Newsflash page) 1 - COR active inside teletext and OSD boxes (Sub-Title / Newsflash page) 0 - TEXT not displayed outside teletext boxes (Sub-Title / Newsflash page) 1 - TEXT displayed outside teletext boxes (Sub-Title / Newsflash page)

50

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add TEXT IN B

PICTURE ON OUT B

PICTURE ON IN B

TXT26

ACH

BIT7

BIT6

BIT5

UOCIII series

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

SHADOW ENABLE B

BOX ON 24 B

BOX ON 1-23 B

BOX ON 0 B

03H

SCR B

SCR B

SCR B

00H

PAGE B

00H

0 - TEXT not displayed inside teletext boxes (Sub-Title / Newsflash page) 1 - TEXT displayed inside teletext boxes (Sub-Title / Newsflash page) 0 - VIDEO not displayed outside teletext boxes (Sub-Title / Newsflash page) 1 - VIDEO displayed outside teletext boxes (Sub-Title / Newsflash page) 0 - VIDEO not displayed inside teletext boxes (Sub-Title / Newsflash page) 1 - VIDEO displayed inside teletext boxes (Sub-Title / Newsflash page) EXTENDED DRCS

TRANS B

0

0

EXTENDED DRCS

0 - Columns 8/9 mapped to DRCS when DRCS characters enabled (32 DRCS characters) 1 - Columns 8/9/A/C mapped to DRCS when DRCS characters enabled (64 DRCS characters)

TRANS ENABLE B

0 - Display black background as normal on Page B 1 - Display black background as video on Page B

SHADOW ENABLE B

BOX ON 24 B

BOX ON 1-23 B

BOX ON 0 B

TXT27

B1H

RDS ON

SCR B

TXT28

ADH

DISPLAY BANK B

PAGE B TXT29

2003 Nov 11

E1H

0 - Disable display of shadow/fringing on Page B 1 - Display shadow/ fringe (default SE black) on Page B 0 - Disable display of teletext boxes in memory row 24 of Page B 1 - Enable display of teletext boxes in memory row 24 of Page B 0 - Disable display of teletext boxes in memory row 1 to 23 of Page B 1 - Enable display of teletext boxes in memory row 1 to 23 of Page B 0 - Disable display of teletext boxes in memory row 0 of Page B 1 - Enable display of teletext boxes in memory row 0 of Page B -

-

-

-

RDS ON

0 - RDS/RBDS disable 1 - RDS/RBDS enable Defines colour to be displayed instead of TV picture and black background for Page B. The bits are equivalent to the RGB components 000 - Transparent 001 - CLUT entry 9 010 - CLUT entry 10 011 - CLUT entry 11 100 - CLUT entry 12 101 - CLUT entry 13 110 - CLUT entry 14 111 - CLUT entry 15 DISPLAY BANK B

DISPLAY BANK B

DISPLAY BANK B

DISPLAY BANK B

PAGE B

PAGE B

PAGE B

0000 - Select Page 0 ~ 9 for Display Page B 0001 - Reserved 0010 - Reserved 0011 - Reserved 0100 - Reserved 0101 - Reserved 0110 - Reserved 0111 - Reserved 1000 - Reserved 1001 - Reserved 1010 - Reserved 1011 - Reserved 1100 - Reserved 1101 - Reserved 1110 - Reserved 1111 - Reserved Current Display page for Page B TEN B

TS B

TS B

OSD PLANES B

OSD LANG ENABLE B

51

CONFIDENTIAL

OSD LAN B

OSD LAN B

OSD LAN B

00H

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add TEN B

TS B OSD PLANES B

OSD LANG ENABLE B

OSD LAN B

TXT30

BIT7

BOTTOM/TOP B

BIT5

BIT4

BIT3

BIT1

BIT0

RESET

STATUS ROW TOP B

DISPLAY X24 B

DISPLAY STATUS ROW ONLY B

00H

GPF

GPF

GPF

GPF

0XH

9FF

9FF

9FF

9FF

XXH

BFE

BFE

BFE

BFE

XXH

BFE

BFE

BFE

BFE

XXH

GPF

GPF

XXH

Twist Character set selection for Page B 0 - Character code columns 8 and 9 defined as single plane characters for Display Page B 1 - Character code columns 8 and 9 defined as double plane characters (special graphics characters) for Display Page B Enable use of OSD LAN to define language option for display, instead of C12/C13/C14 for Display Page B

Alternative C12/C13/C14 bits for use with OSD menus for Display Page B

TC B

TC B

TC B

DOUBLE HEIGHT B

BOTTOM/ TOP B

Language control bits (C12/C13/C14) that has Twisted character set for Page B 0 - Display memory rows 0 to 11 when double height bit is set on Display Page B 1 - Display memory rows 12 to 23 when double height bit is set on Display Page B

DOUBLE HEIGHT B

0 - Display each characters with normal height on Display Page B 1 - Display each character as twice normal height on Display Page B

STATUS ROW TOP B

0 - Display memory row 24 information below teletext page (on display row 24) on Display Page B 1 - Display memory row 24 information above teletext page (on display row 0) on Display Page B

DISLAY X24 B

DISPLAY STATUS ROW ONLY B TXT31

A1H

CC/TXT B

ACTIVE PAGE

1V8GUARD

GPF TXT32

A2H

GPF,9FF TXT33

A3H BFE

TXT34

A4H BFE

TXT35

F7H

9FF, GPF TXT36

FCH BFF

Video_process

2003 Nov 11

A5H

BIT2

0 - Disable Twist function for Page B 1 - Enable Twist character set for Page B

E2H

TC B

BIT6

UOCIII series

0 - Display row 24 from basic page memory on Display Page B 1 - Display row 24 from appropriate location in extension memory on Display Page B 0 - Display normal page rows 0 to 24 on Display Page B 1 - Display only row 24 on Display Page B 0

CC_TXT B

ACTIVE PAGE

1V8GUARD

0 - Display Page B configured for TXT mode 1 - Display Page B configured for CC mode 0 - Display Page A active during two page mode 1 - Display Page B active during two page mode 0 - 1.8V supply is normal 1 - 1.8Vsupply is abnormal (1.44V) General purpose register, bits defined by mask programmable bits GPF

9FF

9FF

9FF

General purpose register, bits defined by mask programmable bits BFE

BFE

BFE

BFE

General purpose register, bits defined by mask programmable bits BFE

BFE

BFE

BFE

General purpose register, bits defined by mask programmable bits 9FF

9FF

9FF

9FF

GPF

GPF

General purpose register, bits defined by mask programmable bits -

-

-

BFF

BFF

BFF

BFF

BFF

XXH

-

-

-

DW_PA

DW_PA

00H

General purpose register, bits defined by mask programmable bits -

-

-

52

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Names

Add DW_PA

WDT

FFH WDV

WDTKEY

FEH WKEY

WSS1

BAH

WSS ERROR

WSS WSS2

BBH

WSS ERROR

WSS WSS3

BCH

WSS ERROR

WSS WSS ERROR

WSS XRAMP

FAH XRAMP

2003 Nov 11

BIT7

BIT6

BIT5

BIT4

UOCIII series

BIT3

BIT2

BIT1

BIT0

RESET

Double Window and Panorama feature selection:00- normal mode (both Double Window and Panorama are disable) 01 - Double Window mode enable; the others are disable 10 - Linear scaling mode enable, the others are disable 11 - non-Linear scaling mode enable, the others are disable WDV

WDV

WDV

WDV

WDV

WDV

WDV

WDV

00H

WKEY

WKEY

WKEY

WKEY

WKEY

WKEY

00H

Watch Dog Timer period WKEY

WKEY

Watch Dog Timer Key Note: Must be set to 55H to disable Watch dog timer when active 0

0

0

WSS ERROR

WSS

WSS

WSS

WSS

00H

0

WSS ERROR

WSS

WSS

WSS

WSS

00H

0 - No error in WSS 1 - Error in WSS Signalling bits to define aspect ratio (group 1) 0

0

0 - No errors in WSS 1 - Error in WSS Signalling bits to define enhanced services (group 2) WSS ERROR

WSS

WSS

WSS

WSS ERROR

WSS

WSS

WSS

00H

XRAMP

XRAMP

XRAMP

XRAMP

XRAMP

00H

0 - No error in WSS 1 - Error in WSS Signalling bits to define reserved elements (group 4) 0 - No error in WSS 1 - Error in WS Signalling bits to define subtitles (group 3) XRAMP

XRAMP

XRAMP

Internal RAM access upper byte address

53

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

External (MOVX) Memory The normal 80C51 external memory area has been mapped internally to the device, this means that the MOVX instruction accesses data memory internal to the device. The movx memory map is shown in Fig.13.

FFH

FFFFH (XRAMP)=FFH

00H FFH

FF00H FEFFH (XRAMP)=FEH

FFFFH

7FFFH

MOVX @Ri, A MOVX A, @Ri

7500H 74FFH

00H

FE00H

FFH

RDS/RBDS Display Data

MOVX @DPTR,A MOVX A,@DPTR

01FFH (XRAMP)=01H

7000H 6FFFH

00H FFH

0100H 00FFH (XRAMP)=00H

9100H 90FFH

Display RAM for TEXT PAGES

00H

Dynamically Re-definable Characters

Fig.14 Indirect addressing (Movx address space)

8800H 87FFH Display Registers 87E0H

Power-on Reset Power on reset is generated internally to the UOCIII device, hence no external reset circuitry is required.

871FH CLUT

2000H

8700H

Software Reset The UOCIII features a software reset (ROMBK SFR, bit 6), which can be used by the micro-controller to reset the following functions/blocks: stereo sound decoder, RDS, ISP, acquisition, display, display RAM and double window/panorama. The software reset is executed by initially setting the corresponding bit to ‘1’ followed by clearing the bit to ‘0’. It takes approximately 200 µs to complete the internal reset sequence.Please note the micro-controller, its peripherals (e.g. timers) and program flash are not reset.

84FFH 0FFFH Data RAM 0000H Lower 32K bytes

0000H

Display RAM for Closed Caption(1) 8000H Upper 32K bytes

(1) Display RAM for Closed Caption, Text, RDS/RBDS is shared

Fig.13 Movx Address Map

Power Saving modes of Operation There are three Power Saving modes, Stand-by, Idle and Power Down, incorporated into the TCG micro-controller (Text/Control/Graphic micro-controller) die. When utilizing either mode, the 3.3V power to the device (Vddp & Vdda) should be maintained. The analogue blocks are powered-down and the clocks to various digital blocks are disabled to minimize the power consumption. The +1.8 V analogue supplies can be switched off.The internally generated 1.8V will be maintained to supply the power of 80c51 and pads.

Auxiliary RAM Page Selection The Auxiliary RAM page pointer is used to select one of the 256 pages within the auxiliary RAM, not all pages are allocated, refer to Fig. 14. A page consists of 256 consecutive bytes. XRAMP only works on internal MOVX memory.

Stand-by Mode During Stand-by mode, the Acquisition, Display, RDS, and SSD sections of the device are disabled. This includes analog modules, such A/D and D/A converter. Before

2003 Nov 11

54

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series • A second method of exiting Idle is via an Interrupt generated by the SAD DC Compare circuit. When TCG micro-controller is configured in this mode, detection of an analogue threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle.

entering standby-mode, the SSD will be allowed to soft-mute the audio outputs. After the required 32 ms, the video processor is powered-down and the following functions remain active:• 80c51 CPU Core • I2C • RCP (Remote Control Pre-processor) • Timer/Counters

• The third method of terminating Idle mode is with a Power On reset. Reset defines all SFRs and Display memory to a pre-defined state, but maintains all other RAM values. Code execution commences with the Program Counter set to ’0000’.

• WatchDog Timer • UART, SAD and PWMs To enter Stand-by mode, the STANDBY bit in the ROMBANK register must be set. The contents of the Display memory are lost. Since the output values on RGB and VDS are maintained the display output must be disabled before entering this mode. This mode should be used in conjunction with both Idle and Power-Down modes. Hence, prior to entering either Idle or Power-Down, the STANDBY bit should be set.

Power Down Mode In Power Down mode the XTAL oscillator is still running. The contents of all SFRs and Data memory are maintained. The port pins maintain the values defined by their associated SFRs. The power down mode is activated by setting the PD bit in the PCON register. It is advised to disable the WatchDog timer prior to entering Power down. Recovery from Power-Down takes several milli-seconds as the oscillator must be given time to stabilize.

Idle Mode During Idle mode, Acquisition, Display, RDS, SSD and the CPU sections of the device are disabled. The following functions remain active:-

There are three methods of exiting power down:•

I2C

• An External interrupt provides the first mechanism for waking from Power-Down. Since the clock is stopped, external interrupts needs to be set level sensitive prior to entering Power-Down. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Power-Down mode.

• RCP • Timer/Counters • WatchDog Timer • UART, SAD and PWMs To enter Idle mode the IDL bit in the PCON register must be set. The WatchDog timer must be disabled prior to entering Idle to prevent the device being reset. It is advice to use the RCP (Remote Control Pre-processor) during the Idle mode to reduce the false interrupt wake-up of 80c51 in order to achieve the low power saving mode. The CPU state is frozen along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values.

• A second method of exiting Power-Down is via an Interrupt generated by the SAD DC Compare circuit. When TCG micro-controller is configured in this mode, detection of a certain analogue threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Power-Down. • The third method of terminating the Power-Down mode is with a Power On reset. Reset defines all SFRs and Display memory, but maintains all other RAM values. Code execution commences with the Program Counter set to ’0000’.

There are three methods available to recover from Idle:• Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Idle mode.

2003 Nov 11

55

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

To accommodate this, another interrupt ET2PR has been added to indicate timer overflow. In addition to the conventional 80c51, four application specific interrupts are incorporated internally to the device which have the following functionality:RDS (Radio Data System Interrupt) - This interrupt is generated when the RDS/RBDS is decoded and available. The interrupt is activated when DAVN (data available) is active which is generated by RDS/RBDS subblock. DET (Supply Dip Monitor Interrupt) - This interrupt is generated when the supply dip monitor detects at dip of 1.44V on one of the 1.8V supply pins. CC (Closed Caption Data Ready Interrupt) - This interrupt is generated when the device is configured for Closed Caption acquisition. The interrupt is activated at the end of the currently selected Slice Line as defined in the CCLIN SFR. BUSY (Display Busy Interrupt) - An interrupt is generated when the Display enters either a Horizontal or Vertical Blanking Period. i.e. Indicates when the micro-controller can update the Display RAM without causing undesired effects on the screen. This interrupt can be configured in one of two modes using the MMR Configuration Register (Address 87FF, Bit-3 [TXT/V]):• TeXT Display Busy: An interrupt is generated on each active horizontal display line when the Horizontal Blanking Period is entered.

I/O Facility I/O PORTS The IC has 24 I/O lines, each is individually addressable, or form part of 4 parallel addressable ports which are port0, port1, port2 and port3. The I/O cells are designed to transfer 3.3V external (Pad side) signals to 1.8V internal (core side) signals, vice versa. And the I/O pads for the bond-out as well as GPIO have 5V tolerant except the I2C clock pad in High-speed mode. PORT TYPE All individual ports can be programmed to function in one of four modes, the mode is defined by two Port Configuration SFRs. The modes available are Open Drain, Quasi-bidirectional, High Impedance and Push-Pull.

Open Drain The Open drain mode can be used for bi-directional operation of a port. It requires an external pull-up resistor, the pull-up voltage has a maximum value of 5.5V, to allow connection of the device into a 5V environment. Quasi bi-directional The quasi-bidirectional mode is a combination of open drain and push pull. It requires an external pull-up resistor to VDDp (nominally 3.3V). When a signal transition from 0->1 is output from the device, the pad is put into push-pull mode for one clock cycle (81.38ns) after which the pad goes into open drain mode. This mode is used to speed up the edges of signal transitions. This is the default mode of operation of the pads after reset.

• Vertical Display Busy: An interrupt is generated on each vertical display field when the Vertical Blanking Period is entered. There are two interrupts connected to the 80c51 micro-controller peripherals as follows: -

High Impedance The high impedance mode can be used for Input only operation of the port. When using this configuration the two output transistors are turned off.

ES2 - I2C Transmit/Receive interrupt. EUART - UART Receive/Transmit interrupt. One additional general purpose external interrupt (EX2) is incorporated into TCG micro-controller and is only available in QFP128 package.

Push-Pull The push pull mode can be used for output only. In this mode the signal is driven to either 0V or VDDp, which is nominally 3.3V.

INTERRUPT ENABLE STRUCTURE Each of the individual interrupts can be enabled or disabled by setting or clearing the relevant bit in the interrupt enable SFRs (IE and IEN1). All interrupt sources can also be globally disabled by clearing the EA bit (IE.7). The EDET interrupt can only be cleared by setting the corresponding status bits in bit 4 and 7 of TXT31 or bit4 and 5 of ROMBK to ’0’.

Interrupt System The device has 12 interrupt sources, each of which can be enabled or disabled. When enabled, each interrupt can be assigned one of two priority levels. There are four interrupts that are common to the 80C51, two of these are external interrupts (EX0 and EX1) and the other two are timer interrupts (ET0 and ET1). The TCG micro-controller family of devices have an additional 24-bit Timer (16-bit timer with 8-bit pre-scaler). 2003 Nov 11

UOCIII series

56

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

Source

EX0 ET0 EX1 ET1 EDET

H1

Highest Priority Level1

L1 H2

Highest Priority Level0

003BH

EUART

UART

004BH

L3 H4

ERDS

falling-edge

0053H

L4 H5

EX2

low-level

005BH

Lowest

Table 7

Interrupt Priority (within same level)

INTERRUPT VECTOR ADDRESS The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The interrupt vector addresses are shown in Table 7.

L9 H10

EUART

falling-edge

0043H

L8 H9

ET2PR

EBUSY

Timer2

L7 H8

EBUSY

Interrupt Vector

ET2PR

L6 H7

ES2

Trigger Condition

L2 H3

L5 H6

ECC

Priority within level

L10 H11 ERDS EX2 Interrupt Source

Source Enable IE.0:6 IEN1.0:4

Global Enable IE.7

L11 H12

Lowest Priority Level1

L12

Lowest Priority Level0

LEVEL/EDGE INTERRUPT The external interrupt (EX0 and EX1) can be programmed to be either level-activated or transition activated by setting or clearing the IT0/1 bits in the Timer Control SFR(TCON).

Priority Control IP.0:6 IP1.0:4

ITx

Fig.15 Interrupt Structure

INTERRUPT ENABLE PRIORITY Each interrupt source can be assigned one of two priority levels (High/Low). The interrupt priorities are defined by the interrupt priority SFRs (IP and IP1). A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt can not be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request with the highest priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as defined in Table 7. Source EX0

Priority within level

0003H

ET0

Timer0

000BH

EX1

low-level or falling-edge

0013H

ET1

Timer1

001BH

EDET

1v8guard

0023H

ECC

high-level

002BH

ES2

low-level

0033H

0

Level, Active Low

1

Edge, Negative Edge

Table 8

External Interrupt Activation

Timer/Counter Two 16 bit timers/counters are incorporated Timer0 and Timer1. Both can be configured to operate as either timers or event counters. In Timer mode, the register is incremented on every machine cycle. It is therefore counting machine cycles. Since the machine cycle consists of 6 oscillator periods, the count rate is 1/6 micro-controller clock(12.288MHz) = 2.048MHz. In Counter mode, the register is incremented in response to a negative transition at its corresponding external pin T0/1. Since the pins T0/1 are sampled once per machine cycle it takes two machine cycles to recognise a transition, this gives a maximum count rate of 1/12 micro-controller clock(12.288MHz)= 1.024MHz. There are six special function registers used to control the timers/counters as defined in Table 9.

Interrupt Vector

low-level or falling-edge

Table 7

Highest

Trigger Condition

Interrupt Type

SFR

Address

TCON

88H

TMOD

89H

TL0

8AH

TH0

8BH

Interrupt Priority (within same level) Table 9

2003 Nov 11

57

CONFIDENTIAL

Timer/Counter Registers

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications SFR

Address

TL1

8CH

TH1

8DH

Table 9

80C51 based 8-bit micro-controllers - Philips Semiconductors (ref. IC20) for detail of the modes and operation. TL0/TL1 and TH0/TH1 are the actual timer/counter registers for timer0 / timer1. TL0/TL1 is the low byte and TH0/TH1 is the high byte.

Timer/Counter Registers

TIMER2 WITH PRE-SCALER An additional 24-bit Timer (16-bit timer with 8-bit pre-scaler) is provided to allow timer periods up to 8.192 seconds. This timer remains active during IDLE mode. TP2L sets the lower value of the period for timer 2 and TP2H is the upper timer value. TP2PR provides an 8-bit pre-scaler for timer 2. The value on TP2PR, TP2H and TP2L shall never change unless updated by the software. If the micro reads TP2R, TP2H orTP2L at any stage, this should return the value written and not the current timer 2 value. The timer 2 should continue after overflow by re-loading (hardware) the timer with the values of SFRs TP2PR, TP2H and TP2L. TP2CL and TP2CH indicate the current timer 2 value. These should be readable both when the timer 2 is active and inactive. Once the timer 2 is disable, the timer 2 value at the time of disabling should be maintained on the SFRs TP2CL and TP2CH. At a count of zero (on TP2CL and TP2CH), the overflow flag should be set:- TP2CRL - ’0’ = no timer 2 overflow, ’1’= timer 2 overflow. TP2CRL is the control and status for timer 2. TP2CRL.0 is the timer enable and TP2CRL.1 is the timer overflow status. The overflow flag will need to be reset by software. Hence, if required, software may poll flag rather than use interrupt. Upon overflow an interrupt should also be generated. Reset values of all registers should be 00 hex.

TF1 TR TF0 TR IE1 IT1 IE0 IT0 Symbol

Position

Name and Significance

TF1

TCON.7

TR1

TCON.6

TF0

TCON.5

TR0

TCON.4

Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 Run control bit. Set/cleared by software to turn timer.counter on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run control bit. Set/cleared by software to turn timer.counter on/off.

Symbol

Position

Name and Significance

IE1

TCON.3

IT1

TCON.2

IE0

TCON.1

IT0

TCON.0

Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Fig.16 Timer/Counter Control (TCON) register

Gat C/T M1 M0 Gat C/T M1 M0 Timer 1 Gate

Timer2 interval = (TP2H * 256 + TP2L) * (TP2PR + 1) * 0.4883us

Timer 0

Gating control when set. Timer/counter is enabled only while external interrupt 0/1 is high and TR control bit is set. When cleared timer/counter is enabled whenever TR control bit is set. Timer or Counter selector. Cleared for timer operation (input from system clock). Set for counter operation (input from T input pin.

C/T

M1

M0

0 0 1

0 1 0

1

1

WatchDog Timer The WatchDog timer is a counter that once in an overflow state forces the micro-controller in to a reset condition. The purpose of the WatchDog timer is to reset the micro-controller if it enters an erroneous processor state (possibly caused by electrical noise or RFI) within a reasonable period of time. When enabled, the WatchDog circuitry will generate a system reset if the user program fails to reload the WatchDog timer within a specified length of time known as the WatchDog interval. The WatchDog timer consists of an 8-bit counter with an 16-bit pre-scaler. The pre-scaler is fed with a signal whose frequency is 1/6 * 12.288MHz = 2.048MHz. The 8 bit timer is incremented every ‘t’ seconds where:

Operating 8048 Timer, TL serves as 5-bit prescaler. 16-bit Timer/Counter, TL and TH are cascaded. 8-bit auto-reload Timer/Counter, TH holds a value which is to be loaded into TL. timer 0: two 8-bit Timers/Counters. TL0 is controlled by timer 0 control bits. TH0 is controlled by timer 1 control bits. timer 1: stopped.

Fig.17 Timer/Counter Mode control (TMOD) The Timer/Counter function is selected by control bits C/T in the Timer Mode SFR (TMOD). These two Timer/Counter have four operating modes, which are selected by bit-pairs (M1.M0) in the TMOD. Refer to the

2003 Nov 11

UOCIII series

t=6x65536x1/12.288x106 = 32ms

58

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications WATCHDOG TIMER OPERATION The WatchDog operation is activated when the WLE bit in the Power Control SFR (PCON) is set. The WatchDog can be disabled by Software by loading the value 55H into the WatchDog Key SFR (WDTKEY). This must be performed before entering Idle/Power Down mode to prevent exiting the mode prematurely. Once activated the WatchDog timer SFR (WDT) must be reloaded before the timer overflows. The WLE bit must be set to enable loading of the WDT SFR, once loaded the WLE bit is reset by hardware, this is to prevent erroneous Software from loading the WDT SFR. The value loaded into the WDT defines the WatchDog interval.

UOCIII series 0.1628us. e.g. if TD = 01H then 1 in 128 periods will be extended by 0.1628us, if TD=02H then 2 in 128 periods will be extended. The TPWM will not start to output a new value until TDACH has been written to. Therefore, if the value is to be changed, TDACL should be written before TDACH. SAD SOFTWARE A/D Four successive approximation Analogue to Digital Converters can be implemented in software by making use of the on board 8-bit Digital to Analogue Converter and Analogue Comparator.

SAD Control The control of the required analogue input is done using the channel select bits CH in the SAD SFR, this selects the required analogue input to be passed to one of the inputs of the comparator. The second comparator input is generated by the DAC whose value is set by the bits SAD in the SAD and SADB SFRs. A comparison between the two inputs is made when the start compare bit ST in the SAD SFR is set, this must be at least one instruction cycle after the SAD value has been set. The result of the comparison is given on VHI one instruction cycle after the setting of ST.

WatchDog interval = (256 - WDT) * t = (256 -WDT) * 32ms.

The range of intervals is from WDT=00H which gives 8.192s to WDT=FFH which gives 32ms. PORT Alternate Functions The Ports 0, 1,2 and 3 are shared with alternate functions to enable control of external devices and circuitry. The alternate functions are enabled by setting the appropriate SFR and also writing a ‘1’ to the Port bit that the function occupies. PWM PULSE WIDTH MODULATORS The device has five 6-bit Pulse Width Modulated (PWM) outputs for analogue control. The PWM outputs generate pulse patterns with a repetition rate of 10.4166us, with the high time equal to the PWM SFR value multiplied by 0.1628us. The analogue value is determined by the ratio of the high time to the repetition time, a D.C. voltage proportional to the PWM setting is obtained by means of an external integration network (low pass filter).

VDDP ADC0 ADC1 MUX ADC2

4-1

ADC3

+ -

CH

PWM Control The relevant PWM is enabled by setting the PWM enable bit PWxE in the PWMx Control register. The high time is defined by the value PWxV

SAD

VHI

8-bit DAC

Fig.18 SAD Block Diagram TPWM TUNING PULSE WIDTH MODULATOR The device has a single 14-bit PWM that can be used for Voltage Synthesis Tuning. The method of operation is similar to the normal PWM except the repetition period is 20.833us.

SAD Input Voltage The external analogue voltage that is used for comparison with the internally generated DAC voltage does not have the same voltage range. The DAC has a lower reference level of VSSA and an upper reference level of VDDA. The resolution of the DAC voltage with a nominal value is 3.3/256 ~= 13mV. The external analogue voltage has a lower value equivalent to VSSA and an upper value equivalent to VDDP - Vtn, were Vtn is the threshold voltage for an NMOS transistor. The reason for this is that the input

TPWM Control Two SFRs are used to control the TPWM, they are TDACL and TDACH. The TPWM is enabled by setting the TPWE bit in the TDACH SFR. The most significant bits TD alter the high period between 0 and 20.833us. The 7 least significant bits TD extend certain pulses by a further 2003 Nov 11

59

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series • F/S-mode (Fast/Standard: 12kHz~384kHz)

pins for the analogue signals (P3.0 to P3.3) are 5V tolerant for normal port operations, i.e. when not used as analogue input. To protect the analogue multiplexer and comparator circuitry from the 5V, a series transistor is used to limit the voltage. This limiting introduces a voltage drop equivalent to Vtn (~0.6V) on the input voltage. Therefore, for an input voltage in the range VDDp to VDDp-Vtn the SAD returns the same comparison value.

Hs-mode can operate up to 2.048 Mbit/s. Fast-mode can operate up to 384kbit/s, which also covers Standard-mode (up to 100kHz). The SCLH-out (Serial CLock line/signal in Hs-mode system) frequency in Hs-mode is specified in SFR, HSBIR, and in F/S-mode is specified in SFR, FSBIR. The micro-controller peripheral is controlled by the Serial Control SFR (S1CON) and its Status is indicated by the status SFR (S1STA). Information is transmitted/received to/from the I2C bus using the Data SFR (S1DAT) and the Slave Address SFR (S1ADR) is used to configure the slave address of the peripheral.

SAD DC Comparator Mode The SAD module incorporates a DC Comparator mode which is selected using the ’DC_COMP’ control bit in the SADB SFR. This mode enables the micro-controller to detect a threshold crossing at the input to the selected analogue input pin (P3.0, P3.1, P3.2 or P3.3) of the Software A/D Converter. A level sensitive interrupt is generated when the analogue input voltage level at the pin falls below the analogue output level of the SAD D/A converter. This mode is intended to provide the device with a wake-up mechanism from Power-Down or Idle when a key-press on the front panel of the TV is detected. The following software sequence should be used when utilizing this mode for Power-Down or Idle:1. Disable INT1 using the IE SFR.

Hs-mode The various serial rates are shown below: -

Reload-value in HSBIR

MOD_CLK divided by

MOD_CLK=12.288MHz

0

3

not allowed

1

6

2.048MHz

2

9

1.365MHz

3

12

1.024MHz

2. Set INT1 to level sensitive using the TCON SFR.

4

15

0.819MHz

3. Set the D/A Converter digital input level to the desired threshold level using the SAD/SADB SFRs and select the required input pin (P3.0, P3.1, P3.2 or P3,3) using CH1, CH0 in the SAD SFR.

5

18

0.6875MHz

6

21

0.585MHz

7

24

0.512MHz

|

|

|

4. Enter DC Compare mode by setting the ’DC_COMP’ enable bit in the SADB SFR.

|

|

|

31

96

0.128MHz

5. Enable INT1 using the IE SFR. Table 10 I2C Serial Rates ‘Hs-mode’

6. Enter Power-Down/Idle. Upon wake-up the SAD should be restored to its conventional operating mode by disabling the ’DC_COMP’ control bit. I2C Serial I/O Bus The I2C bus consists of a serial data line (SDA) and a serial clock line (SCL). The definition of the I2C protocol can be found in The I2C-bus Specification v2.1, January 2000, Philips Semiconductor. The device operates in four modes: • Master Transmitter • Master Receiver • Slave Transmitter • Slave Receiver Each of the 4 modes above can operate at the next speed modes: • Hs-mode (High speed: 128kHz~2.048MHz) or 2003 Nov 11

60

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

The 80c51 Micro-controller incorporates a full duplex UART with a single byte receive buffer, meaning that it commence reception of a second byte before the first is read form the receive buffer. The UART’s RX and TX pins connect to P1.4 & P1.5 respectively. Two registers (S0CON, S0BUF) control the UART along with SMOD bit of PCON register: -

F/S mode Reload-value in FSBIR

MOD_CLK divided by

MOD_CLK=12.288MHz

0

8

not allowed

1

16

not allowed

2

24

not allowed

3

32

384kHz

4

40

307kHz

5

48

256kHz

6

56

219kHz

7

64

192kHz

8

72

170.65kHz

9

80

168.75kHz

|

|

|

12

104

118.15kHz

|

|

14

120

102.4kHz

15

128

96kHz

|

|

|

24

200

61.45kHz

|

|

|

33

272

45.2kHz

|

|

|

37

304

40.4kHz

|

|

|

49

400

30.7kHz

|

|

|

127

1024

12kHz

UOCIII series

SFR

Address

PCON

87H

S0CON

99H

S0BUF

9AH

Table 12 UART Special Function Registers S0CON The serial port control and status register is the Special Function Register S0CON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).

Table 11 I2C Serial Rates ‘F/S mode’1 1. F/S-SCL frequencies between 0 and 100 kHz are allowed if the F/S bit in FSBIR is ’0’ (Standard mode); F/S-SCL frequencies between 0 and 400kHz are allowed if the F/S-bit in FSBIR is ’1’ (Fast mode).

I2C Port Enable One external I2C port is available. This port is enabled using TXT21.I2C PORT EN. Any information transmitted to the device can only be acted upon if the port is enabled. Internal communication between the 80c51 micro-controller and the TV Signal Processor will continue regardless of the value written to TXT21.I2C PORT EN. I2S Port Enable Five external I2S port are available. Each port is enabled using I2S.EN_I2SDI1, I2S.EN_I2SDO1, I2S.EN_I2SDO2, I2S.EN_I2SCLK, and I2S.EN_I2SWS. Any information transmitted/received to/from the device can only be activated upon if the port is enabled. UART Peripheral 2003 Nov 11

61

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

SM0

SM1

SM2

Symbol SM0 SM1 SM2

Position S0CON.7 S0CON.6 S0CON.5

REN

S0CON.4

Symbol TB8

Position S0CON.3

RB8

S0CON.2

TI

S0CON.1

REN

TB8

RB8

TI

Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/6 the frequency of clk. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (’0’), 8 data bits (LSB first), and a stop bit (’1’). On receive, the stop bit goes into RB8 in Special Function Register S0CON. The baud rate is determined by the Timer 1 overflow rate. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (’0’), 8 data bits (LSB first), a 9th data bit, and a stop bit (’1’). On Transmit, the 9th data bit, TB8 in S0CON, can be assigned the value of ’0’ or ’1’. For example, the parity bit could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the frequency of the micro-controller clock. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (’0’), 8 data bits (LSB first), a 9th data bit, and a stop bit (’1’). In fact, mode 3 is the same as mode 2 in all respects except baud rate. The baud rate is determined by the Timer 1 overflow rate.

RI

Name and Significance Mode selection bit 0. Mode selection bit 1. Enables the multi processor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if the received 9th data bit is ’0’. In mode 1, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if no valid stop bit was received. In mode 0, SM2 has no influence. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Name and Significance Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 is ’0’, RB8 is the stopbit that was received. In mode 0, RB8 is not used. Loading of RB8 in modes 1, 2 and 3 depends on SM2. Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the

In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in mode 0 by the condition RI = ’0’ and REN = ’1’. In the other modes reception is initiated by the incoming start bit if REN = 1. UART Multi-Processor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th bit goes into RB8, followed by a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = ’1’. This feature is enabled by setting bit SM2 in S0CON. A way to use this feature in multi-processor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte. The 9th bit is ’1’ in an address byte and ’0’ in a data byte. With SM2 = ’1’, no slave will be interrupted by a data byte reception. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will follow. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the incoming data bytes. SM2 has no effect in mode 0, and in mode 1 it can be used to check the validity of the stop bit. When receiving in

Fig.19 S0CON Special Function Registers

S0BUF This register is implemented twice. Writing to S0BUF writes to the transmit buffer. Reading from S0BUF reads from the receive buffer. Only hardware can read from the transmit buffer and write to the receive buffer. SMOD bit of PCON SMOD is the double baud rate bit. If SMOD=’1’ the baud rate in mode 1, 2 and 3 is doubled. In mode 0 SMOD is not used. UART Modes The serial port can operate in 4 modes: -

2003 Nov 11

UOCIII series

62

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series Remote Control Pre-processor The remote control pre-processor is used to reduce the number of wake-up’s for the 80c51 core (from IDLE mode).

mode 1, if SM2 = ’1’, the receive interrupt will not be activated unless a valid stop bit is received. S0BUF Registers This register is implemented twice. Writing to S0BUF writes to the transmit buffer. Reading from S0BUF reads from the receive buffer. Only hardware can read from the transmit buffer and write to the receive buffer.

To Start the remote control pre-processor, bit 7 of RCP6 register (SFR address EEH), must be programmed to ‘1’. Afterward, SW has to program the RCP-SFRs:•

UART Baud Rates NOTE: fclk used in the following calculations refers to the micro-controller clock frequency (12.288MHz). The serial port can operate with different baud rates depending on its mode. The baud rate in mode 0 is derived from state 2 and state 5 and thus fixed: Mode 0 baud rate = fclk/ 6 The baud rate in mode 2 depends on the value of bit SMOD.

• •



Clock divider rate CDIV (= divider between Xtal and RCP counter) AL = 75% of the nominal, shortest allowable LOW pulse AH = 125% of the nominal, longest allowable pulse MINUS AL (saves timer span & is easier for SW) BL, BH = same as AL, AH, but then for the HIGH time of the pulse

Because RC5 does not have a real start-pulse (long, with other timing) the registers AL, AH, BL, BH don’t have to be written every pulse transition.

If SMOD = 0, the baud rate is fclk/32 If SMOD = 1, the baud rate is fclk/16

Further the SW (re-)programs: SMOD

Mode 2 baud rate =

2 ------------------ × f clk 32



The baud rates in mode 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: • SMOD

Mode 1, 3 baud rate =

2 ------------------ × ( Timer1OverflowRate ) 32

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either ’timer’ or ’counter’ operation, and in any of its 3 running modes. In the most typical applications, it is configured for ’timer’ operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate =

NGP = 0 -> the flag that tells the RCP-HW has found a timing-error (not in the first pulse) and so the RC5 message string decoding must be terminated. NFP = 0 -> means the RCP-HW is “hunting” for the first pulse. If there occurs a timing-error during the first pulse, the micro gets NO wake-up interrupt. The RCP keeps hunting for a pulse that matches the “start-pulse-timing”. (= ideal for protocols with a ling start-pulse). The RCP-HW sets NFP=1, to signal that the first (start-) pulse was found. Further NFP=1 takes care that any following-pulse-with-error ALWAYS generates a wake-up interrupt (terminate decoding).

Now the SW goes to sleep in IDLE mode. The Xtal clock continues, watchdog timer, timer & RCP keep working (with same Xtal frequency).

SMOD f clk 2 ------------------ × -----------------------------------------32 6 × ( 256 – T1H )

One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload.

When an RC-INT arrives, the micro-core wake-up in STANDBY mode. Now the SW must read the RCP results from RA, RB (two 12-bits, folded into 3 SFRS:- RCP3, RCP4, and RCP5) plus the error flags NFP and NGP. (note that after the FIRST pulse, the RCP-HW will always come back with NGP=0).

For further details on the UART operation refer to “80C51 Based 8-Bit Micro-controllers - Philips Semiconductors (ref. IC20).

When there is an error (NGP=1), then the RC-string decoding must be terminated (i.e. further, trailing bits will make an the following string an invalid one).

2003 Nov 11

63

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications With NO-ERROR the SW only has to check if RA and RB are longer than 1x tp (minus 75% of the shortest allowable pulse=AL) which show whether the pulse had a width of 1x tp or 2x tp.

UOCIII series At the END of an RC5 string there is a special condition: a LOW-pulse, followed by a HIGH data-clean time (>2.5tp), WITHOUT subsequent interrupt. A simple solution is to load the BH register BEFORE the last pulse with 3xtp (minus AL). As a consequence you will get an INT after 3tp data clean time: in this special case NGP=1 shows during 3tp nothing has happened, to the message has ended OK.

This simplifies the decoding SW considerably (timing errors are already checked by RCP-HW), for RC5 the bi-phase decoding-method is similar to the older SW. If an error NGP=1 is received, then break-off the decoding and let SW set NFP=0, so that the HW starts hunting again for the FIRST pulse.

The following table shows the timing characteristics of some existing Remote Control Protocols:-

Name

RC5

Sony

NEC

Motorola

Japan

Daewoo

Samsung

Denon

Startbit

889us

2.4ms

9ms

3ms

3.38ms

8ms

4.5ms

-

Shortest

889us

600us

560us

512us

420us

450us

560us

275us

Longest

1178us

1.2ms

1.69ms

1024us

1.27ms

1.45ms

1.69ms

1.9ms

Repeat

113.8ms

45ms

67.5ms

34ms

90ms

60ms

60ms

65ms

Table 13 Remote Control Protocols I2S Clock Output Selection The I2S Clock output can be selected via I2S.I2S_CLK SFRs. The output clock is shown in below:fs=32kHz I2S.I2S_CLK

I2S Clock Output

00

256fs

01

128fs

10

64fs

11

not allowed

information that has been requested. The Display reads the SRAM information and converts it to RGB output values. The display RAM is initialized on power-on to a value of 20H throughout. The contents of the display RAM is not maintained when entering power saving modes (stand-by, idle, and power-down). Upon leaving standby mode and resuming normal operation, the display RAM is initialized to a value of 20H throughout again (by hardware). The same applies when a software reset is issued. In this case, the display RAM is initialized to 20H throughout as well. The Display RAM occupies a maximum of 20K with an address range from 2000H to 6FFFH; the TXT14. DISPLAY BANK and TXT15.MICRO BANK must keep default value “0000”. The RDS/RBDS Display Data occupies 1.25K with an address range from 7000H to 74FF H. The three modes although having different address ranges occupy physical the same SRAM area. When TXT27.RDS ON = 1, the RDS/RBDS Display memory would map to the physical SRAM area. When TXT27.RDS ON=0, TXT21.CC/TXT=1 / 0, then the CC / TXT memory would map to the physical SRAM area.

Table 14 I2S Clock Output Selection LED Support All port pins have a 4mA current sinking capability to enable LEDs in series with current limiting resistors to be driven directly, without the need for additional buffering circuitry.

Data Capture The Data Capture section takes in the analogue Composite Video and Blanking Signal (CVBS) from Video Signal Processor, and from this extracts the required data, which is then decoded and stored in SFR or memory.

SRAM MEMORY INTERFACE The SRAM memory interface controls the access to the embedded SRAM and page clearing. The SRAM is shared between Data Capture and Display sections. The Data Capture section uses the SRAM to store acquired 2003 Nov 11

64

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications The extraction of the data is performed in the digital domain. The first stage is to convert the analogue CVBS signal into a digital form. This is done using an ADC sampling at 12.288MHz. The data and clock recovery is then performed by a Multi-Rate Video Input Processor (MulVIP). From the recovered data and clock the following data types are extracted WST Teletext (625/525),Closed Caption, VPS, WSS(625). The extracted data is stored in either memory (SRAM) via the SRAM Memory Interface or in SFR locations.

UOCIII series Data Standards The data and clock standards that can be recovered are shown in Table 15 below:-

Data Capture Features • Video Signal Quality detector. • Data Capture for 625 line WST

Data Standard

Clock Rate

625WST

6.9375 MHz

525WST

5.7272 MHz

VPS

5.0 MHz

625WSS

5.0 MHz

Closed Caption

500 KHz

Table 15 Data Slicing Standards

• Data Capture for 525 line WST

Data Capture Timing The Data Capture timing section uses the Synchronisation information extracted from the CSI signal to generate the required Horizontal and Vertical reference timings. The timing section automatically recognises and selects the appropriate timings for either 625 (50Hz) synchronisation or 525 (60Hz) synchronisation. A flag TXT12.Video Signal Quality is set when the timing section is locked correctly to the incoming CVBS signal. When TXT12.Video Signal Quality is set another flag TXT12.625/525 SYNC can be used to identify the standard.

• Data Capture for US Closed Caption • Data Capture for VPS data (PDC system A) • Data Capture for 625 line Wide Screen Signalling (WSS) bit decoding • Automatic selection between 525 WST/625WST • Automatic selection between 625WST/VPS on line 16 of VBI • Real-time capture and decoding for WST Teletext in Hardware, to enable optimized microprocessor throughput • Up to 10 pages stored On-Chip

Acquisition The acquisition sections extracts the relevant information from the serial stream of data from the MulVIP and stores it in memory.

• Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) • Automatic detection of FASTEXT transmission

625 WST ACQUISITION The family is capable of acquiring 625-line and 525-line World System Teletext. Teletext pages are identified by seven numbers: magazine (page hundreds), page tens, page units, hours tens, hours units, minutes tens and minutes units. The last four digits, hours and minutes, are known as the subcode, and were originally intended to be time related, hence their names.

• Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters • Signal quality detector for WST/VPS data types • Comprehensive Teletext language coverage • Vertical Blanking Interval (VBI) data capture of WST data Analogue to Digital Converter The CVBS input is passed through a differential to single ended converter (S/D-Conv+Level-shift). The analogue output of S/D-Conv+Level-shift is converted into a digital representation by a Video ADC with a sampling rate of 12.288MHz.

Making a page request A page is requested by writing a series of bytes into the TXT3.PRD SFR which correspond to the number of the page required. The bytes written into TXT3 are stored in a RAM with an auto-incrementing address. The start address for the RAM is set using the TXT2.SC to define which part of the page request is being written, TXT2.ACQ_BANK and TXT3.ACQ_BANK are used to define which bank and TXT2.REQ is used to define which of the 10 page requests in the selected bank

Multi Rate Video Input Processor The multi rate video input processor is a Digital Signal Processor designed to extract the data and recover the clock from the digital CVBS signal. 2003 Nov 11

65

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

and to display each page header as it arrives until the correct page has been found. When a page request is changed (i.e.: when the TXT3 SFR is written to) a flag (PBLF) is written into bit 5, column 9, row 25 of the corresponding block of the page memory. The state of the flag for each block is updated every TV line, if it is set for the current display block, the acquisition section writes all valid page headers which arrive into the display block and automatically writes an alpha-numerics green character into column 7 of row 0 of the display block every TV line. When a requested page header is acquired for the first time, rows 1 to 23 of the relevant memory block are cleared to space, i.e.: have 20h written into every column, before the rest of the page arrives. Row 24 is also cleared if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF bit is set the extension packets corresponding to the page are also cleared. The last 8 characters of the page header are used to provide a time display and are always extracted from every valid page header as it arrives and written into the display block The TXT0. DISABLE HEADER ROLL bit prevents any data being written into row 0 of the page memory except when a page is acquired off air i.e.: rolling headers and time are not written into the memory. The TXT1.ACQ OFF bit prevents any data being written into the memory by the teletext acquisition section. When a parallel magazine mode transmission is being received only headers in the magazine of the page requested are considered valid for the purposes of rolling headers and time. Only one magazine is used even if don't care magazine is requested. When a serial magazine mode transmission is being received all page headers are considered to be valid.

is being modified. If TXT2.REQ is greater than 09h, then data being written to TXT3 is ignored. Table 16 shows the contents of the page request RAM. Up to 10 pages of teletext can be acquired on the 10 page device when TXT1.EXT PKT OFF is set to logic 1; and up to 9 pages can be acquired when this bit is set to logic 0. If the 'Do Care' bit for part of the page number is set to 0 then that part of the page number is ignored when the teletext decoder is deciding whether a page being received off air should be stored or not. For example, if the Do Care bits for the 4 subcode digits are all set to 0 then every subcode version of the page will be captured. Start Column

Byte Identification

PRD

PRD

PRD

PRD

PRD

0

Magazine

DO CARE

HOLD

MAG2

MAG1

MAG0

1

Page Tens

DO CARE

PT3

PT2

PT1

PT0

2

Page Units

DO CARE

PU3

PU2

PU1

PU0

3

Hours Tens

DO CARE

x

x

HT1

HT0

4

Hours Units

DO CARE

HU3

HU2

HU1

HU0

5

Minutes Tens

DO CARE

x

MT2

MT1

MT0

6

Minutes Units

DO CARE

MU3

MU2

MU1

MU0

7

Error Mode

x

x

x

E1

E0

Table 16 The contents of the Page request RAM Note: MAG = Magazine PT = Page Tens PU = Page Units HT = Hours Tens HU = Hours Units MT = Minutes Tens MU = Minutes Units E = Error check mode When the Hold bit is set to 0 the teletext decoder will not recognise any page as having the correct page number and no pages will be captured. In addition to providing the user requested hold function this bit should be used to prevent the inadvertent capture of an unwanted page when a new page request is being made. For example, if the previous page request was for page 100 and this was being changed to page 234, it would be possible to capture page 200 if this arrived after only the requested magazine number had been changed. The E1 and E0 bits control the error checking which should be carried out on packets 1 to 23 when the page being requested is captured. This is described in more detail in a later section (‘Error Checking’). For a multi page device, each packet can only be written into one place in the teletext RAM so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request. At power-up each page request defaults to any page, hold on and error check mode 0.

Error Checking Before teletext packets are written into the page memory they are error checked. The error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. If uncorrectable errors are detected in any other Hamming checked data the byte is not written into the memory.

Rolling Headers and Time When a new page has been requested it is conventional for the decoder to turn the header row of the display green

2003 Nov 11

UOCIII series

Teletext Memory Organisation The teletext memory is divided into 10 banks of 10 blocks. Normally, when the TXT1.EXT PKT OFF bit is logic 0, 66

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the ‘subtitle’ page header control bit (C6) set.The bit for a particular page in the TPT is set when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the ‘subtitle’ page header control bit (C6) set.

each of blocks 0 to 8 contains a teletext page arranged in the same way as the basic page memory of the page device and block 9 contains extension packets. When the TXT1.EXT PKT OFF bit is logic 1, no extension packets are captured and block 9 of the memory is used to store another page. The number of the memory block into which a page is written corresponds to the page request number which resulted in the capture of the page. Packet 0, the page header, is split into 2 parts when it is written into the text memory. The first 8 bytes of the header contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25. Row 25 also contains the magazine number of the acquired page and the PBLF flag but the last 14 bytes are unused and may be used by the software, if necessary.

Packet 26 Processing One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. The family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. This is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default character data over writing the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten. This mechanism is disabled when the Spanish national option is detected as the Spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations corresponding to the characters sent via packet 26 and these will not over write the packet 26 characters anyway. The special treatment of Spanish national option is prevented if TXT12. ROM VER R4 is logic 0 or if the TXT8.DISABLE SPANISH is set. Packet 26 data is processed regardless of the TXT1. EXT PKT OFF bit, but setting theTXT1.X26 OFF disables packet 26 processing. The TXT8. Packet 26 received bit is set by the hardware whenever a character is written into the page memory by the packet 26 decoding hardware. The flag can be reset by writing a 0 into the SFR bit.

Row 25 Data Contents The Hamming error flags are set if the on-board 8/4 Hamming checker detects that there has been an uncorrectable (2 bit) error in the associated byte. It is possible for the page to still be acquired if some of the page address information contains uncorrectable errors if that part of the page request was a 'don't care'. There is no error flag for the magazine number as an uncorrectable error in this information prevents the page being acquired. The interrupted sequence (C9) bit is automatically dealt with by the acquisition section so that rolling headers do not contain a discontinuity in the page number sequence. The magazine serial (C11) bit indicates whether the transmission is a serial or a parallel magazine transmission. This affects the way the acquisition section operates and is dealt with automatically. The newsflash (C5), subtitle (C6), suppress header (C7), inhibit display (C10) and language control (C12 to 14) bits are dealt with automatically by the display section, described below. The update (C8) bit has no effect on the hardware. The remaining 32 bytes of the page header are parity checked and written into columns 8 to 39 of row 0. Bytes which pass the parity check have the MSB set to 0 and are written into the page memory. Bytes with parity errors are not written into the memory.

In the first edition of ETS 300 706, the “@” symbol is available for display at level 1 only when: 1). the page uses the Latin G0 set and selects the English national option set, or 2). when the Hebrew G0 character set is selected. The device will also display @ in response to the packet 26 triplet containing NULL accent (mode value 10000) and character 4/0 providing the Latin G0 set is currently selected. The * character is available as a level 1 character in all of the defined G0 character sets and it is very unlikely that a * character would be invoked at level 1.5 via the triplet NULL accent, character 2/A. Therefore, the second edition

Inventory Page If the TXT0.INV on bit is 1, memory block 8 is used as an inventory page. The inventory page consists of two tables, - the Transmitted Page Table (TPT) and the subtitle page table (SPT). In each table, every possible combination of the page tens and units digit, 00 to FFh, is represented by a byte. Each bit of these bytes corresponds to a magazine number so each page number, from 100 to 8FF, is represented by a bit in the table.The bit for a particular page in the TPT is set 2003 Nov 11

UOCIII series

67

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications of ETS 300 706 defines that the @ symbol should be displayed in response to the NULL accent, character 2/A triplet for all G0 character set. The IC will display the * character while providing * is sent as the fallback character on the level 1 page, and depend on the software (DDS) to implement the first edition of ETS 300 706 which should also display *, or the second edition of ETS 300 706 which should display the @ symbol.

version of the packet are the same so they are stored whenever either version of the packet is acquired. In 525 line text each packet 26 only contains ten 24/18 Hamming encoded data triplets, rather than the 13 found in 625 line text. The tabulation bit is used as an extra bit (the MSB) of the designation code, allowing 32 packet 26s to be transmitted for each page. The last byte of each packet 26 is ignored. FASTEXT DETECTION When a packet 27, designation code 0 is detected, whether or not it is acquired, the TXT13. FASTEXT bit is set. If the device is receiving 525 line teletext, a packet X/0/27/0 is required to set the flag. The flag can be reset by writing a 0 into the SFR bit.

525 WST The 525 line format is similar to the 625 line format but the data rate is lower and there are less data bytes per packet (32 rather than 40). There are still 40 characters per display row so extra packets are sent each of which contains the last 8 characters for four rows. These packets can be identified by looking at the ‘tabulation bit’ (T), which replaces one of the magazine bits in 525 line teletext. When an ordinary packet with T = 1 is received, the decoder puts the data into the four rows starting with that corresponding to the packet number, but with the 2 LSBs set to 0. For example, a packet 9 with T = 1 (packet X/1/9) contains data for rows 8, 9, 10 and 11. The error checking carried out on data from packets with T = 1 depends on the setting of the TXT1. 8 BIT bit and the error checking control bits in the page request data and is the same as that applied to the data written into the same memory location in the 625 line format. The rolling time display (the last 8 characters in row 0) is taken from any packets X/1/1, 2 or 3 received. In parallel magazine mode only packets in the correct magazine are used for rolling time. Packet number X/1/0 is ignored. The tabulation bit is also used with extension packets. The first 8 data bytes of packet X/1/24 are used to extend the Fastext prompt row to 40 characters. These characters are written into whichever part of the memory the packet 24 is being written into (determined by the ‘X24 Posn’ bit). Packets X/0/27/0 contain 5 Fastext page links and the link control byte and are captured, Hamming checked and stored by in the same way as are packets X/27/0 in 625 line text. Packets X/1/27/0 are not captured. Because there are only 2 magazine bits in 525 line text, packets with the magazine bits all set to 0 are referred to as being in magazine 4. Therefore, the broadcast service data packet is packet 4/30, rather than packet 8/30. As in 625 line text, the first 20 bytes of packet 4/30 contain encoded data which is decoded in the same way as that in packet 8/30. The last 12 bytes of the packet contains half of the parity encoded status message. Packet 4/0/30 contains the first half of the message and packet 4/1/30 contains the second half. The last 4 bytes of the message are not written into memory. The first 20 bytes of the each

2003 Nov 11

UOCIII series

BROADCAST SERVICE DATA DETECTION When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525 line transmission, the TXT13. Packet 8/30. The flag can be reset by writing a 0 into the SFR bit. The data of packet 8/30 is written to the block 9. VPS ACQUISITION When the TXT0. VPS ON bit is set, any VPS data present on line 16, field 0 of the CVBS signal at the input of the teletext decoder is error checked and stored in row 25, block 9 of the basic page memory. The device automatically detects whether teletext or VPS is being transmitted on this line and decodes the data appropriately.

column

0 Teletext page row 25 header data

9 10 11

VPS byte 11

12 13 14

15 16 17 18 19 20 21

VPS VPS byte 12 byte 13

VPS VPS byte 14 byte 15

VPS byte 4

22 23 VPS byte 5

Fig.20 VPS Data Storage Each VPS byte in the memory consists of 4 bi-phase decoded data bits (bits 0-3), a bi-phase error flag (bit 4) and three 0s (bits 5-7). The TXT13. VPS Received bit is set by the hardware whenever VPS data is acquired. The flag can be reset by writing a 0 into the SFR bit.

625 WSS ACQUISITION The Wide Screen Signalling data transmitted on line 23 gives information on the aspect ratio and display position of the transmitted picture, the position of subtitles and on the camera/film mode. Some additional bits are reserved for future use. A total of 14 data bits are transmitted. All of the available data bits transmitted by the Wide Screen

68

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

Signalling signal are captured and stored in SFRs WSS1, WSS2 and WSS3. The bits are stored as groups of related bits and an error flag is provided for each group to indicate when a transmission error has been detected in one or more of the bits in the group. Wide screen signalling data is only acquired when the TXT8.WSS ON bit is set. The TXT8.WSS RECEIVED bit is set by the hardware whenever wide screen signalling data is acquired. The flag can be reset by writing a 0 into the SFR bit.

RDS_Subsystem The RDS_SUBSYSTEM contains Serialiser, RDS demodulator, and RDS/RBDS decoder.

CLOSED CAPTION ACQUISITION The US Closed Caption data is transmitted on line 21 (525 line timings) and is used for Captioning information, Text information and Extended Data Services. Closed Caption data is only acquired when TXT21.CC ON bit is set. Two bytes of data are stored per field in SFRs, the first bye is stored in CCDAT1 and the second byte is stored in CCDAT2. The value in the CCDAT registers are reset to 00h at the start of the Closed Caption line defined by CCLIN.CS. At the end of the Closed Caption line an interrupt is generated if IE.ECC is active. The processing of the Closed Caption data to convert into a displayable format is performed by Software.

DEMODULATOR The RDS demodulator regenerates the raw RDS bit stream (bit rate=1187.5 Hz) from the modulated RDS signal in two steps. The first step is the demodulation of the Double-Side-Band Suppressed-Carrier signal around 57 kHz into a baseband signal, by carrier extraction and down-mixing. The second step is the BPSK demodulation of the biphase coded baseband signal, by clock extraction and correlation. The raw RDS bit stream data is provided for further processing by the RDS/RBDS decoder block.

Serialiser The RDS Serialiser converts the 304kHz 10-bits parallel data to 9.728MHz 32-bits serial data (10-bits data, 22-bits dummy). The output bitstream data of the Serialiser will then feed to Demodulator.

DECODER The RDS/RBDS decoder handles the complete data processing and decoding of the continuously received serial RDS/RBDS demodulator output data stream. Different data processing modes are software controllable via SFRs. The RDS/RBDS decoder provides the RDS/RBDS block detection, error detection, error correction, synchronization, flywheel for synchronization hold, and programmable block data output. New processed RDS/RBDS block information is signalled (interrupt) to the micro-controller as “new data available” by use of the DAVN output. The block data and the corresponding status information will be output to the RDS SFRs and can be read out by micro-controller via SFR Interface. The processing of the RDS/RBDS data to convert into a displayable format is performed by Software.

RDS/RBDS The Radio Data System (RDS)/ Radio Broadcast Data System (RBDS) informations are carried in FM radio channels. The FM radio channels are located in the range from 87.5MHz to 108MHz. Once a radio channel is tuned, the MPX signal is processed by this block. RDS/RBDS Features • Demodulation of the European Radio Data System (RDS) or the USA Radio Broadcast Data System (RBDS) signal • RDS and RBDS block detection • Error detection and correction • Fast block synchronization

RDS/RBDS Block Detection The RDS/RBDS block detection is always active. For a received sequence of 26 data bits a valid block and corresponding offset are identified via syndrome calculation. During synchronization search, the syndrome is calculated with every new received data bit (bit-by-bit) for a received 26-bit sequence. If the decoder is synchronized, syndrome calculation is activated only after 26 data bits for each new block received. Under RBDS reception situation, besides the RDS block sequences with (A, B, C/C’, D) offset also block sequences of 4 blocks with offset E may be received. If the decoder detects an ‘E-block’, the block is marked in the block

• Synchronization control (flywheel) • Mode control for RDS/RBDS processing • Different RDS/RBDS block information output modes Analogue to Digital Converter The RDS input is passed to a single ended to differential converter (S/D-conv+L-shift). The analogue output of S/D-conv+L-shift is converted into a digital representation by a Video ADC with a sampling rate of 304kHz.

2003 Nov 11

69

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

carried out until the first valid and error free block has been received. Then the next expected block calculated and syndrome calculation is done after the next 26 bits have been received. The block-span in which the second valid and expected block can be received is selectable via previously setting of the Max_Bad_Blocks_Gain (MBBG). If the second received block is an invalid block, then the bad_blocks_counter is incremented and again the new next expected block is calculated. If the bad_blocks_counter value reaches the pre-selected Max_Bad_Blocks_Gain, then the bit-by-bit search for the first block is started again. If synchronization is found, the synchronization status flag (SYNC) is set and available via SFR read. The synchronization is held until the bad_blocks_counter value reaches the pre-selected Max_Bad_Blocks_Lose value (used for synchronization hold) or an external restart of synchronization is performed (NWSY=1; or power-on reset).

identification number (BlNr) and is stored in the SFR LBIN. In RBDS processing mode the block is signalled as valid ‘E-block’ and in RDS processing mode, where only RDS blocks are expected, signalled as invalid ‘E-block’. This information can be used by the micro-controller to detect ‘E-block’ sequences and identify RDS or RBDS transmitter stations.

Error Detection and Correction The RDS/RBDS error detection and correction recognizes and corrects potential transmission errors within a received block via parity-check in consideration of the offset word of the expected block. Burst errors with a maximum length of 5 bits are corrected with this method. After synchronization has been found the error correction is always active depending on the pre-selected ‘error correction mode of synchronization’ (mode SYNCA ... SYNCD), but cannot be carried out in every reception situation. During synchronization search, the error correction is disable for detection of the first block and is enable for processing of the second block depending on the pre-selected ‘error correction mode for synchronization’ (mode SYNCA ... SYNCD). The processed block data and the status of error correction are stored in the SFRs (Status Registers). EXB1

EXB0

Description

0

0

no errors detected

0

1

burst error of max. 2 bits corrected

1

0

burst error of max. 5 bits corrected

1

1

uncorrectable block

FLYWHEEL FOR SYNCHRONIZATION HOLD For a fast detection of loss of synchronization an internal flywheel shall be implemented. Therefore one counter (bad_blocks_counter) checks the number of uncorrectable blocks and a second counter (good_blocks_counter) checks the number of error free or correctable blocks. Error blocks increment the bad_blocks_counter and valid blocks increment the good_blocks_counter. If the counter value of the good_blocks_counter reaches the pre-selected Max_Good_Blocks_Lose value (MGBL the good_blocks_counter and bad_blocks_counter are reset to zero. But if the bad_blocks_counter reaches the pre-selected Max_Bad_Blocks_Lose value (MBBL) then new synchronization search (bit-by-bit) is started (SYNC=0) and both counters are reset to zero. The flywheel function is only activated if the decoder is synchronized. The synchronization is held until the bad_blocks_counter reaches the pre-selected Max_Bad_Blocks_Lose value (loss of synchronization) or an external forced start of new synchronization search (NWSY=1) is performed. The maximum values for the flywheel counters are both adjustable via SFR in a range of 0 to 63.

Table 17 RDS processed error correction Processed blocks are characterized as uncorrectable under the following conditions: • During synchronization search, if the burst error (for the second block) is higher than allowed by the pre-selected correction mode SYNCA ... SYNCD. • After synchronization has been found, if the burst error exceeds the correctable max. 5 bit burst error or if errors are detected but error correction is not possible.

Bit Slip Correction During poor reception situation phase shifts of one bit to the left or right (+/- 1 bit slip) between the RDS/RBDS clock and data may occur, depending on the lock conditions of the demodulator clock regeneration. If the decoder is synchronized and detects a bit slip (BSLP=1), the synchronization is corrected +1, 0 or -1 bit via block detection on the respectively shifted expected new block.

Synchronization The decoder is synchronized if two valid blocks in a valid sequence are detected by the block detection. The search for the first block is done by a bit-by-bit syndrome calculation, starting after the first 26 bits have been received. This bit-by-bit syndrome calculation is

2003 Nov 11

UOCIII series

70

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Data Processing Control The decoder should provide different operating modes selectable by NWSY, SYM0, SYM1, DAC0 and DAC1 inputs via the SFRs. The data processing control performs the pre-selected operating modes and controls the requested output of the RDS/RBDS information.

RBDS Processing Mode The decoder should be suitable for receivers intended for the European (RDS) as well as for the USA (RBDS) standard. If RBDS mode is selected (RBDS=1) via the SFR, the block detection and the error detection and correction are adjusted to RBDS data processing. That is, also E blocks are treated as valid blocks. If RBDS is reset to zero (RDS_CTRL.RBDS=0), RDS mode is selected.

Restart of Synchronization Mode The ‘restart synchronization’ (NWSY) control mode immediately terminates the actual synchronization and restarts a new synchronization search procedure (NWSY=1). The NWSY flag is automatically reset after the restart of synchronization by decoder (NWSYRe pulse). This mode is required for a fast new synchronization on the RDS/RBDS data from a new transmitter station if the tuning frequency is changed by the radio set. Restart of synchronization search is furthermore automatically carried out if the internal flywheel signals a loss of synchronization.

Data Available Control Modes The decoder provides three different RDS/RBDS data output processing modes plus one decoder bypass mode selectable via the ’data available’ control mode inputs DAC0 and DAC1.

Error Correction Control Mode For Synchronization For error correction and identification of valid blocks during synchronization search as well as synchronization hold, four different modes are selectable (SYM, SYM). • mode SYNCA (SYM=0, SYM=0): no error correction; blocks detected as correctable are treated as invalid blocks internal bad_blocks_counter still incremented even if correctable errors detected. If synchronized only error free blocks increment the good_blocks_counter. All blocks except error free blocks increment the bad_blocks_counter. • mode SYNCB (SYM=0, SYM=1): error correction of burst error max. 2 bits; blocks corrected are treated as valid blocks, all other errors detected are treated as invalid blocks. If synchronized error free and correctable max. 2 bit error increment the good_blocks_counter.

mode DAVA: (DAC1=0, DAC0=0)

Standard output mode: If the decoder is synchronized and a new block is received (every 26 bits), the actual RDS/RBDS information of the last two blocks is available with every new received block (approx. every 21.9ms).

mode DAVB: (DAC1=0, DAC0=1)

Fast PI search mode: During synchronization search and if a new A or C’ block is received, the actual RDS/RBDS information of this or the last two A or C’ blocks respectively is available with every new received A or C’ block. If the decoder is synchronized, the "standard output mode" is active.

mode DAVC: (DAC1=1, DAC0=0)

Reduced data request output mode: If the decoder is synchronized and two new blocks are received (every 52 bits), the actual RDS/RBDS information of the last two blocks is available with every two new received blocks (approx. every 43.8ms).

mode DAVD: (DAC1=1, DAC0=1)

Decoder bypassed mode: If this mode is selected then the OutMux output of the decoder is reset to low (OutMux=0). Then the internal row buffer output is active and the decoder is bypassed. This mode is not available in normal application mode.

Table 18 DAV Modes The decoder provides:- data output of the block-identification of the last and previously processed blocks, the RDS/RBDS information words and error detection/correction status of the last two blocks as well as general decoder status information. In addition the decoder output is controlled indirectly by the data request (SFR read) by micro-controller. The decoder receives a ‘data overflow’ (DOFL) signal controlled by the SRF. This DOFL signal has to be set to high (DOFL=1) if the decoder is synchronized and a new RDS/RBDS block is received before the previously processed block was completely transmitted via SFRs. After detection of data overflow the SFRs are not updated (no DecWrE) until reset of the data overflow flag (DOFL=0) by reading via the SFRs or if NWSY=1 which results in start of new synchronization search (SYNC=0).

• mode SYNCC (SYM=1, SYM=0): error correction of burst error max. 5 bits; blocks corrected are treated as valid blocks, all other errors detected are treated as invalid blocks. If synchronized error free and correctable max. 5 bit error increment the good_blocks_counter. • mode SYNCD (SYM=1, SYM=1): no error correction; blocks detected as correctable are treated as invalid always incremented even if correctable errors detected. If synchronized error free blocks are correctable max. 5 bit errors increment the good_blocks_counter. Only uncorrectable blocks increment the bad_blocks_counter.

2003 Nov 11

UOCIII series

71

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

Data Output of RDS/RBDS Information The decoded RDS/RBDS block information and the current decoder status should be available via the SFRs. For synchronization of data request between micro-controller and decoder the additional data available output (DAVN) is used for the interrupt. For DAVN timing information see next section. If the decoder has processed new information for the micro-controller the data available signal (DAVN) is activated (low) under the following condition:• During synchronization search in DAVB mode if a valid A or C’ block has been detected. This mode can be used for fast search tuning (detection and comparison of the PI code contained in the A and C’ blocks.

• If the decoder is synchronized and in DAVC mode two new blocks have been processed.

• During synchronization search in any DAV mode except DAVD mode, if two blocks in the correct sequence have been detected (synchronization criterion fulfilled).

DAVN Timing The processed RDS/RBDS data are available for micro-controller request for at least 20ms after the DAVN signal was activated. The DAVN signal is always automatically de-activated (high) after ~ 10ms.

• If the decoder is synchronized and in any DAV mode except DAVD mode loss of synchronization is detected (flywheel loss of synchronization, resulting in restart of synchronization search). • In any DAV mode except DAVD mode, if a reset caused by power-on or voltage-drop is detected (PresN=0). • Remark: If the decoder is synchronized, the DAVN signal is always activated after 21.9ms in DAVA or DAVB mode and after 43.8ms in DAVC mode independent of valid or invalid blocks are detected.

• If the decoder is synchronized and in mode DAVA and DAVB a new block has been processed. This mode is the standard output mode, if the decoder is synchronized.

The decoder ignores new processed RDS/RBDS blocks if the DAVN signal is active (low).

Fig.21 DAVN LOW-time (decoder is synchronized)

RDS SFRs SYMBOL

PARAMETER

Typical

UNIT

tDVL

data valid to DAVN LOW

2.0

us

tTDAV

data valid period

21.9

ms

tDV

data valid

21.9

ms

tDAVL

data available signal is LOW

10.1

ms

CONTROL REGISTER The RDS has 4 input control registers to which can be written by the micro-controller via the MOVX. The RDS provides 3 different RDS/RBDS data output processing modes plus one decoder module bypass mode selectable via the control registers DAC. The NWSY control signal is to start new synchronization process, if set to high. This bit of the control register is

Table 19 Data Available Signal (DAVN)

2003 Nov 11

72

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

demodulator module) clock pulses and has to be used directly as RSTD register-flag set signal. Last block identification number, LBIN hold the block number of the last processed RDS/RBDS data block. The LBIN are controlled by the output signals, BlNr, of decoder module. The LBIN registers has to be connected to the inputs of the register(PBlN) which holds the previously processed block number. So if RCopyE is set to high while DecWrE is active a copy from the last to the previously block number will be done. Error status of last block, ELB, these registers are controlled by the output signals, EXB1 & EXB0. The ELB holds the error status of the last processed RDS/RBDS data block. The output of these registers has to be connected to the input of the register (EPB) which holds the previously processed error status. So, if RCopyE is set to high while DecWrE is active a copy from the last to the previously error status will be done. Bad block counter registers, BBC, represent the actual bad_blocks_counter value. Good block counter registers, GBC, represent the actual good_blocks_counter value.

reset to low with a positive NWSYRe output pulse generated automatically by the decoder module. The maximum invalid blocks allowed during synchronization search (SYNC=0). If the first block needed for synchronization has been found and the expected second block (after 26 bits) is an invalid block, then the decoder module internal_bad_blocks_counter is incremented and the next expected block is calculated; exception: if RBDS mode is selected and the first block is block E, then the next expected block is always block A, until synchronization is found or the maximum bad_blocks_counter value is reached. If the decoder module internal bad_blocks_counter reaches the value of the MBBG, then immediately start of new synchronization search (bit-by-bit) is started to find a new first block. The function of Max_Bad_Blocks_Gain is disable if MAX_Bad_Blocks_Gain is set to zero. Only in this case the 2 path synchronization search function is activated. For error correction and identification of valid blocks during synchronization search as well as synchronization hold, 4 different modes are selectable (SYM, SYM). MBBL - Max_Bad_Blocks_Lose: maximum invalid blocks allowed while synchronized (SYNC=1). If the decoder module internal bad_blocks_counter reaches this value, then immediately start of “new synchronization search” (bit-by-bit) is started (SYNC=0) and the internal bad_blocks_counter as well as the good_blocks_counter itself are reset to zero. MGBL - Max_Good_Blocks_Lose: maximum valid blocks required to clear the decoder module internal bad_blocks_counter. Only activated while synchronized (SYNC=1). If the decoder module internal good_blocks_counter reaches this value, then immediately the bad_blocks_counter and the good_blocks_counter itself are reset to zero. RBDS - If this bit set to high, then allow processing of RBDS ‘E’ block. Otherwise, if set to low, it will enter RDS mode.

RDS/RBDS DECODED DATA REGISTER The decoder module has 4 output registers to put the processed/decoded RDS/RBDS block data. These registers can be read by the micro-controller after detection of the RDS interrupt (DAVN=low). Last processed data, LDAT, hold the parallel output of the 16 bit from Data decoder module output bus, which represents the information word of the last processed RDS/RBDS data block. The output of this registers has to be connected to the input of the register PDAT which holds the previously processed block data. So if RCopyE is set to high while DecWrE is active a copy from the last to the previously block will be done. DISPLAY The display section is based on the requirements for a Level 1.5 WST Teletext and US Closed Caption. There are some enhancements for use with locally generated On-Screen Displays. The display section reads the contents of the Display memory and interprets the control/character codes. Using this information and other global settings, the display produces the required RGB signals and Video/Data (Fast Blanking) signal for the TV signal processing. The display is synchronised to the TV signal processing by way of Horizontal and Vertical sync signals generated within UOCIII. From these signals all display timings are derived.

STATUS REGISTER The RDS module has one status register. The output signal, SYNC, from decoder module indicates the synchronization found. It is set high, if synchronization is found; otherwise reset to zero. The SYNC output signal directly effects the status register. RSTD is set to high, if a reset occurred, caused by power-on reset or voltage drop. RSTD register is set by SRSTD signal output from decoder module. The RSTD status flag has to be cleared automatically after the status register was read by micro-controller. SRSTD is set to high (after power-on reset) for the first received 26 RDCL(from

2003 Nov 11

UOCIII series

73

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

device.The display is configured as a fixed 25 rows with 40 characters per row.

Display Features • Teletext and Enhanced OSD modes • Level 1.5 WST features

• CC:- This is the display configured as the US Closed Caption mode with the same functionality as the PC83C771 device. The display is configured as a maximum of 16 rows with a maximum of 48 characters per row.

• US Closed Caption Features • 50Hz/60Hz display timing modes • Two page operation for 16:9 screens • Serial and Parallel Display Attributes

• OSD:-This is the display configured as either TXT or CC mode but without the restriction of display size or character matrix.

• Single/Double/Quadruple Width and Height for characters • Smoothing capability of both Double Size, Double Width & Double Height characters

There is an option of 10/13/16/18 lines per display row for CC style OSD mode, the characters used in these rows can be either 12x13, 12x16, 12X18, 16X16, 16x18. In CC style OSD mode the number of rows and columns available in limited by the maximum row value of 16, the maximum column value of 48 and the maximum number of character location of 624. This gives a full occupied display of 16 rows by 39 columns for maximum rows, or 13 rows by 48 columns for maximum columns. In TXT style OSD mode the maximum number of rows is 25 and the maximum number of columns is 40, both of these limits can be achieved simultaneously. Note: Not all combinations of lines per row and maximum display rows give a sensible OSD display, since there is limited number of TV scan lines available. Special Function Register, TXT21 and memory mapped register are used to control the mode selection.

• Scrolling of display region • Variable flash rate controlled by software • Globally selectable scan lines per row 9/10/13/16/18. • Globally selectable character matrix (HxV) 12x9/10, 12x13, 12x16, 16x16 and 16x18 • Italics, Underline and Overline • Soft Colours using CLUT with 4096 colour palette. • Fringing (Shadow) selectable from N-S-E-W direction. • Fringe colour selectable • Contrast reduction of defined area is available in both TXT and CC mode • Double window • Cursor

The following is a list of features available in each mode. Each setting can either be a serial or parallel attribute, and some have a global effect on the display.

• Special Graphics characters with two planes, allowing four colours per character • 64 Software re-definable DRCs (Dynamically Re-definable Characters), when it’s used as 4 colour mode for each pixel, the number of DRCs will be 32 • 4 WST Character sets(G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) • G1 Mosaic graphics, Limited G3 Line drawing characters • WST Character sets and Closed Caption Character set in single device • Panorama Mode, display 4:3 signals on 16:9 screen • SCAVEM for Text Display Modes The display section has three distinct modes with different features available in each. The two modes are: • TXT:- This is the display configured as the WST mode with additional serial and global attributes to enable the same functionality as the SAA5497 (ETT)

2003 Nov 11

UOCIII series

Feature

TXT

CC

Flash

serial

serial

Boxes

TXT/OSD (Serial)

serial

Horizontal Size

x1/x2/x4 (serial)

x1/x2 (serial)

Vertical Size

x1/x2 (serial) x4 (global)

x1/x2 (serial)

Italic

N/A

serial

Foreground colours

8 (serial)

8+8 (parallel)

Background colours

8 (serial)

16 (serial)

Soft Colours (CLUT)

16 from 4096

16 from 4096

Table 20 Display Features

74

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Feature

TXT

CC

Underline

N/A

serial

Overline

N/A

serial

Fringe

N+S+E+W

N+S+E+W

Fringe Colour

16 (Global)

16 (Serial)

Smoothing

YES (Global)

YES (Global)

Fast Blanking Polarity

YES

YES

Screen Colour

16 (Global)

16 (Global)

DRCS

64 (Global)

64 (Global)

Character Matrix (HxV)

12x9/10/13/16

12x9/10/13/16, 16x16/18

No. of Rows

25

16

No. of Columns

40

48

No of Characters displayable

1000

624

Cursor

YES

YES

Special Graphics (2 planes per character)

32

32

Scroll

NO

YES

mode the background colour is displayed. Character locations where boxes are not set show video/screen colour (depending on the setting in the display control register. REG0: Display Control) in stead of the background colour. TXT: Two types of boxes exist the Teletext box and the OSD box. The Teletext box is activated by the ‘start box’ control character (0Bh), Two start box characters are required begin a Teletext box, with box starting between the 2 characters. The box ends at the end of the line or after a ‘end box’ control character. TXT mode can also use OSD boxes, they are started using size implying OSD control characters (BCh/BDh/BEh/BFh). The box starts after the control character (‘set after’) and ends either at the end of the row or at the next size implying OSD character (‘set at’). The attributes flash, teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an OSD box, as they are at the start of the row. OSD Boxes are only valid in TV mode which is defined by TXT5=03h and TXT6=03h. SIZE The size of the characters can be modified in both the horizontal and vertical directions. CC: Two sizes are available in both the horizontal and vertical directions. The sizes available are normal (x1), double (x2) height/width and any combination of these. The attribute setting is always valid for the whole row. Mixing of sizes within a row is not possible. TXT: Three horizontal sizes are available normal(x1),double(x2),quadruple(x4). The control characters ‘normal size’ (0Ch/BCh) enables normal size, the ‘double width’ or double size (0Eh/BEh/0Fh/BFh) enables double width characters. Any two consecutive combination of ‘double width’ or ‘double size’ (0Eh/BEh/0Fh/BFh) activates quadruple width characters, provided quadruple width characters are enabled by TXT4.Quad Width Enable. Three vertical sizes are available normal(x1), double(x2), quadruple(x4). The control characters ‘normal size’ (0Ch/BCh) enable normal size, the ‘double height’ or ‘double size’ (0Dh/BDh/0Fh/BFh) enable double height characters. Quadruple height character are achieved by using double height characters and setting the global attributes TXT7.Double Height (expand) and TXT7.Bottom/Top. If double height characters are used in teletext mode, single height characters in the lower row of the double height character are automatically disabled.

Table 20 Display Features Display Feature Descriptions FLASH Flashing causes the foreground colour pixel to be displayed as the background pixels.The flash frequency is controlled by software setting and resetting display register REG0: Status at the appropriate interval. CC: This attribute is valid from the time set (see Table 27) until the end of the row or until otherwise modified. TXT: This attribute is set by the control character ‘flash’ (08h) and remains valid until the end of the row or until reset by the control character ‘steady’ (09h). BOXES CC: This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then it is set from the next character onwards. In CC text mode the background colour is displayed regardless of the setting of the box attribute bit. Boxes take affect only during mixed mode, where boxes are set in this 2003 Nov 11

UOCIII series

75

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

writing data to a RAM that resides in the MOVX address space of the 80C51.

ITALIC CC: This attribute is valid from the time set until the end of the row or otherwise modified. The attribute causes the character foreground pixels to be offset horizontally by 1 pixel per 4 scan lines (interlaced mode). The base is the bottom left character matrix pixel. The pattern of the character is indented as shown in Fig.22 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 1 12x16 character matrix 2 3 4 5 6 7 8 9 10 11 12 13 14 15

12x10 character matrix

12x13 character matrix

UOCIII series

Indented by 7/6/4

RED3-0 b11. . .b4

GRN3-0 b7. . .b4

BLU3-0 b3. . .b0

0000

0000

0000

0

0000

0000

1111

1

...

...

...

...

1111

1111

0000

14

1111

1111

1111

15

Indented by 6/5/3 Indented by 5/4/2 Indented by 4/3/1

Table 21 CLUT Colour values

Indented by 3/2/0 Indented by 2/1 Indented by 1/0 Indented by 0

Field 1 Field 2

Italy Shift Indented by 10 Indented by 9 Indented by 8 Indented by 7 Indented by 6 Indented by 5 Indented by 4 Indented by 3 Indented by 2 Indented by 1 Indented by 0

Scan Line -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pixels 0

Character Size

4 2

8 6

0

2

4 6

10 12 14 16 Wide x 18 High

Fig.22 Italic Characters TXT: The Italic attribute is not available. COLOURS

CLUT (Colour Look Up Table) A CLUT (Colour Look Up Table) with 16 colour entries is provided. The colours are programmable out of a palette of 4096(4 bits per R, G and B). The CLUT is defined by

2003 Nov 11

Colour entry

76

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications The default value of the CLUT when entering TXT mode is given in the table below, this gives the required full intensity teletext colours.

Full Intensity Equivalent (Foreground)

CLUT Address

UOCIII series Serial Mode 1, then the colour is set from the next character onwards. The background colour can be chosen from all 16 CLUT entries. TXT: The control character “New background” (“1Dh”) is used to change the background colour to the current foreground colour. The selection is immediate (“Set at”) and remains valid until the end of the row or until otherwise modified. The TEXT background control characters map to the CLUT entries as shown below:

Full Intensity Equivalent (Background)

CLUT Address

Default

0

000000000000

Black

8

000000000000

Black

1

111100000000

Red

9

111100000000

Red

2

000011110000

Green

A

000011110000

Green

3

111111110000

Yellow

B

111111110000

Yellow

Control Code

Defined Colour

CLUT Entry

4

000000001111

Blue

C

000000001111

Blue

00h+1Dh

Black

8

5

111100001111

Magenta

D

111100001111

Magenta

01h+1Dh

Red

9

6

000011111111

Cyan

E

000011111111

Cyan

02h+1Dh

Green

10

7

111111111111

White

F

111111111111

White

03h+1Dh

Yellow

11

04h+1Dh

Blue

12

05h+1Dh

Magenta

13

06h+1Dh

Cyan

14

07h+1Dh

White

15

Default

Table 22TXT Default CLUT map

Foreground Colour CC: The foreground colour can be chosen from 8 colours on a character by character basis. Two sets of 8 colours are provided. A serial attribute switches between the banks (see Table 27 Serial Mode 1, bit 7). The colours are the CLUT entries 0 to 7 or 8 to 15. TXT: The foreground colour is selected via a control character. The colour control characters takes effect at the start of the next character (“Set-After”) and remain valid until the end of the row, or until modified by a control character. Only 8 foreground colours are available. The TEXT foreground control characters map to the CLUT entries as shown below: Control Code

Defined Colour

CLUT Entry

00h

Black

0

01h

Red

1

02h

Green

2

03h

Yellow

3

04h

Blue

4

05h

Magenta

5

06h

Cyan

6

07h

White

7

Table 24 Background CLUT mapping BACKGROUND DURATION The attribute when set takes effect from the current position until to the end of the text display defined in REG4:Text Area End. CC: The background duration attribute (see Table 27, Serial Mode 1, bit 8) in combination with the End Of Row attribute (see Table 27, Serial Mode 1, bit 9) forces the background colour to be display on the row until the end of the text area is reached. TXT: This attribute is not available. UNDERLINE The underline attribute causes the characters to have the bottom scan line of the character cell forced to foreground colour, including spaces. If background duration is set, then underline is set until the end of the text area. CC: The underline attribute (see Table 27, Serial Mode 0/1, bit 4) is valid from the time set until end of row or otherwise modified. TXT: This attribute is not available.

Table 23 Foreground CLUT mapping

OVERLINE The overline attribute causes the characters to have the top scan line of the character cell forced to foreground colour, including spaces. If background duration is set, then overline is set until the end of the text area.

Background Colour CC: This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with 2003 Nov 11

77

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series defined by TXT10.C. The position of the cursor can be fixed using TXT9.CURSOR FREEZE. CC: The valid range for row is 0 to 15. The valid range for column is 0 to 47. The cursor remains rectangular at all times, it’s shape is not affected by italic attribute, therefore it is not advised to use the cursor with italic characters. TXT: The valid range for row positioning is 0 to 24.The valid range for column is 0 to 39.

CC: The overline attribute (see Table 27, Serial Mode 0/1, bit 5) is valid from the time set until end of row or otherwise modified. Overlining of Italic characters is not possible. TXT: This attribute is not available. END OF ROW CC: The number of characters in a row is flexible and can determined by the end of row attribute (see Table 27, Serial Mode 1, bit 9). However the maximum number of character positions displayed is determined by the setting of the REG2:Text Position Horizontal and REG4:Text Area End. NOTE: When using the end of row attribute the next character location after the attribute should always be occupied by a ’space’. TXT: This attribute is not available, Row length is fixed at 40 characters.

ABCDEF Fig.24 Cursor Display SPECIAL GRAPHICS CHARACTERS -Normal Special Graphics character Mode(TXT20.Extended special graphics = 0) CC/TXT: Several special characters are provided for improved OSD special effects. These characters provide a choice of 4 colours within a character cell. Addressing is therefore done using only the even character addresses. The total number of special graphics characters is limited to max. 32 when Extended Special Graphics is not enabled. They are stored in the character codes 8Xh, 9Xh of the character table (32 ROM characters), or in the DRCs which overlay character codes 8Xh, 9Xh, AXh and CXh (if Extended DRC is enabled). Each special graphics character uses two consecutive normal characters. The pixel planes are stored in adjacent characters, always starting with an even character. Special graphics characters are activated when TXT20/TXT29.OSD_PLANE = 1.

FRINGING A fringe (shadow) can be defined around characters. The fringe direction is individually selectable in any of the North, South, East and West direction using REG3:Fringing Control. The colour of the fringe can also be defined as one of the entries in the CLUT, again using REG3:Fringing Control. CC: The fringe attribute (see Table 27, Serial Mode 0, bit 9) is valid from the time set until the end of the row or otherwise modified. TXT: The display of fringing in TXT mode is controlled by the TXT4.SHADOW bit. When set all the alphanumeric characters being displayed are shadowed, graphics characters are not shadowed.

-Extended Special Graphics character Mode(TXT20.Extended special graphics = 1) CC:- When "TXT20.Extended special graphics" is enabled, all characters from the ROM can be used as special graphics characters in this mode. Each special graphics character uses two consecutive characters from the normal Character Set. Closed Caption character code bit-14 enables display of special graphics on a character by character basis. Fig.23 South and Southwest Fringing

note: Special Graphics capability extended to any character only in Closed_Caption Mode

CURSOR The cursor operates by reversing the background and foreground colours in the character position pointed to by the active cursor position. The cursor is enabled using TXT7.CURSOR ON. When active, the row the cursor appears on is defined by TXT9.R and the column is 2003 Nov 11

Four-colour on-screen display characters can be created in closed caption and teletext style sets, provided they are either 12x13 or 16x16 or16x18 characters. Four-colour characters are generated by overlaying two consecutive

78

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications two-colour characters. For example see following figure. The two characters on the left could overlap to produce the four-colour character on the right. For the character definition the black would represent a 1 and the white would represent a 0. Four-colour characters can easily be defined using the DDS tool. The character is defined on a pixel-by-pixel basis, after checking four colours option.

UOCIII series Height, Double Width and Double Size Characters are all improved when smoothing is enabled. Character and Attribute Coding CC MODE Character coding is split into character oriented attributes (parallel) and character group coding (serial). The serial attributes take effect either at the position of the attribute (Set At), or at the following location (Set After) and remain effective until either modified by a new serial attribute or until the end of the row. A serial attribute is represented as a space (the space character itself however is not used for this purpose), the attributes that are still active, e.g. overline and underline will be visible during the display of the space. The default setting at the start of a row is: • 1x size, flash and italics OFF

The colours here have been used for the example. Four colours are achieved by using the foreground and the background colours, for example CLUT entries 0 and 1, and the default (for four-colour characters) CLUT entries 6 and 7. In your application software you will need to define the CLUT Table entries to obtain the colours that you require and the foreground and the background colours. Plane 1

Plane 0

Colour

Colour Allocation

0

0

Blue

Background Colour

• Display mode = superimpose

0

1

White

Foreground Colour

• fringing OFF

1

0

Red

CLUT Entry 6 or 14 depending on the set bank

1

1

Green

CLUT Entry 7 or 15 depending on the set bank

• overline and underline OFF

• background colour duration = 0 • end of row = 0 The coding is done in 15 bit words. The codes are stored sequentially in the display memory. A maximum of 768 character positions can be defined for a single display.

Table 25 Special Character Colour allocation PARALLEL CHARACTER CODING . Background Colour “set at” (Mode 0)

Serial Attribute

Background Colour “set after” (Mode 1)

VOLUME

Bits

Description

0-7

8 bit character code

8-10

3 bits for 8 foreground colours

11

Mode bit: 0 = Parallel code

12-13

Character Select Selection: 00 = Character Set 0

Foreground Colour Background Colour Normal Character Foreground Colour 7

01 = Character Set 1 10 = Character Set 2 Foreground Colour 6

11 = Character Set 3

Special Character

14

Character Definition: 0 = Single Plane Character

Fig.25 Special Character Example

1 = Two Plane Character (four colour)

Table 26 Parallel Character Coding

The example in Fig.25 can be done with 8 special graphics characters. Smoothing Smoothing is available in both TXT and CC modes and is activated using MMR 87E4. The clarity of Double 2003 Nov 11

79

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

SERIAL CHARACTER CODING

Bits

Description Serial Mode 0 (“set at”)

Serial Mode 1 Char.Pos. 1 (“set at”)

Char.Pos. >1 (“set after”)

0-3

4 bits for 16 Background colours

4 bits for 16 Background colours

4 bits for 16 Background colours

4

0 = Underline OFF 1 = Underline ON

Horizontal Size: 0 = normal 1 = x2

0 = Underline OFF 1 = Underline ON

5

0 = Overline OFF 1 = Overline ON

Vertical Size: 0 = normal 1 = x2

0 = Overline OFF 1 = Overline ON

6

Display mode: 0 = Superimpose 1 = Boxing

Display mode: 0 = Superimpose 1 = Boxing

Display mode: 0 = Superimpose 1 = Boxing

7

0 = Flash OFF 1 = Flash ON

Foreground colour switch 0 = Bank 0 (colours 0-7) 1 = Bank 1 (colours 8-15)

Foreground colour switch 0 = Bank 0 (colours 0-7) 1 = Bank 1 (colours 8-15)

8

0 = Italics OFF 1 = Italics ON

Background colour duration: 0 = stop BGC 1 = set BGC to end of row

Background colour duration (set at): 0 = stop BGC 1 = set BGC to end of row

9

0 = Fringing OFF 1 = Fringing ON

End of Row 0 = Continue Row 1 = End Row

End of Row (set at): 0 = Continue Row 1 = End Row

10

Switch for Serial coding mode 0 and 1:

Switch for Serial coding mode 0 and 1:

Switch for Serial coding mode 0 and 1:

0 = mode 0

1 = mode 1

1 = mode 1

Mode bit:

Mode bit:

Mode bit:

1 = Serial code

1 = Serial code

1 = Serial code

0 = Cont. Red. OFF 1 = Cont. Red. ON

0 = Cont. Red. OFF 1 = Cont. Red. ON

0 = Cont. Red. OFF 1 = Cont. Red. ON

11

12

Table 27 Serial Character Coding

Bits 12/13 of the parallel character coding are used to select the character set on character by character basis. In CC Mode only, bits 13 and 12 of character code can

Character ROM Selection in CC Mode

2003 Nov 11

80

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications control the character set selection when TXT20 is set. When TXT20 is reset to ’0’ the normal BS bits(TXT18) control character set selection as for Text mode.

attribute will behave in exactly the same fashion as the background colour attribute. The actual contrast reduction is carried out in the Video Signal Processor die and is simply switched in and out by the cont_red signal from TCG micro-controller. The effect of contrast reduction is to reduce the brightness and contrast of the video image behind the OSD. For this reason, contrast reduction is only visible in mixed screen mode with superimposed text.

In table 28 shows the character set selection. Although the hardware allow to select from 4 character sets, due to the DDS tool limitation the Set 0 is only for teletext.

CC Mode Char code

character Set

Example Language

00

Set 0

Latin

01

Set 1

Greek

10

Set 2

Cyrillic

11

Set 3

Arabic

UOCIII series

TXT MODE Character coding is in a serial format, with only one attributes being changed at any single location. The serial attributes take effect either at the position of the attribute (Set At), or at the following location (Set After). The attribute remains effective until either modified by new serial attributes or until the end of the row.The default settings at the start of a row is: • foreground colour white (CLUT Address 7) • background colour black (CLUT Address 8) • Horizontal size x1, Vertical size x1 (normal size)

Table 28 Character Set Selection

• Alphanumeric ON

Serial mode 0 Serial mode 0 means that these attributes are valid from the time set until the end of the row or until otherwise modified. This differs from serial mode 1, where they are valid from the next character onwards.

• Contiguous Mosaic Graphics • Release Mosaics • Flash, Box, Conceal and Twist OFF The attributes have individual codes which are defined in the basic character table below:

Serial mode 1 Serial mode 1 means that these attributes are valid from the character following the character code until the end of the row or until otherwise modified. This differs from serial mode 0 where they are also valid for the character code itself. However, for the first character of each line, serial mode 1 behaves differently. When a serial mode 1 character code is set in position 1 of a line, attributes are valid from the time set as in mode 0. There is also a different set of attributes. All but two of these attributes are the same as for the rest of the line. The two different attributes are horizontal and vertical size, bits 4 and 5 respectively. These replace Underline and Overline. Contrast Reduction in CC Mode When bit 12 of the serial character coding is set, this generates a contrast reduction box. By setting TXT5 bits 5 and 4, contrast reduction can be enabled inside, or outside, these boxes. When contrast reduction is active, the cont_red output signal is set low. The cont_red signal is always synchronized with VDS. With regard to interaction with other features, the contrast reduction

2003 Nov 11

81

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

b7 b6 b5 b4

0

bits

b3 b2 b1 b0

column

row 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 0

0

0

0 0

0

1

alpha black alpha red alpha green alpha yellow alpha blue alpha magenta alpha cyan alpha white

graphics black graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display contiguous graphics separated graphics

flash steady end box start box normal height double height double width double size

0

1

0 1

0

UOCIII series

0 0 0 0 10 1 1 1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 01 0 1 1 0 1 1 0 0 1 0

2 2a 3 3a 4 5 6 6a 7 7a 8 8a 9 9a A Nat Opt

Nat Opt

Nat Opt Nat Opt

twist

Nat Opt

Nat Opt

black bkgnd new bkgnd hold graphics release graphics

Nat Opt

Nat Opt

Nat Opt

Nat Opt

Nat Opt

Nat Opt

Nat Opt

O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D O O O O S S S S D D D D

B bkgnd black bkgnd red bkgnd green bkgnd yellow bkgnd blue bkgnd magenta bkgnd cyan bkgnd white

norm sz OSD dbl ht OSD dbl wd OSD dbl sz OSD

Fig.26 TXT Basic Character Set (Pan-European)

2003 Nov 11

82

CONFIDENTIAL

C

E/W = 0

E/W = 1

11 11 11 0 1 1 1 0 1

11 11 11 0 1 1 1 0 1

D E F

D E F

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Screen and Global Controls A number of attributes are available that affect the whole display region, and cannot be applied selectively to regions of the display.

UOCIII series

Display Mode

TV SCAN LINES PER ROW The number of TV scan lines per field used for each display row can be defined, the value is independent of the character size being used. The number of lines can be either 10/13/16 per display row. The number of TV scan lines per row is defined TXT21.DISP_LINES. A value of 9 lines per row can be achieved if the display is forced into 525 line display mode by TXT17.DISP_FORCE, or if the device is in 10 line mode and the automatic detection circuitry within display finds 525 line display syncs. CHARACTER MATRIX (HXV) There are five different character matrices available, these are 12x13, 12x16, 16x16 and 16x18. The selection is made using TXT21.CHAR_SIZE and is independent of the number of display lines per row. If the character matrix is less than the number of TV scan lines per row then the matrix is padded with blank lines. If the character matrix is greater than the number of TV scan lines then the character is truncated.

MOD

Description

Video

0 0

Video mode disables all display activities and sets the RGB to true black and VDS to video.

Full Text

0 1

Full Text mode displays screen colour at all locations not covered by character foreground or background colour. The box attribute has no effect.

Mixed Screen Colour

1 0

Mixed Screen mode displays screen colour at all locations not covered by character foreground, within boxed areas or, background colour.

Mixed Video

1 1

Mixed Video mode displays video at all locations not covered by character foreground, within boxed areas or, background colour.

Table 29 Display Modes TXT: The display mode is controlled by the bits in the TXT5 and TXT6. There are 3 control functions - Text on, Background on and Picture on. Separate sets of bits are used inside and outside Teletext boxes so that different display modes can be invoked. TXT6 is used if the newsflash (C5) or subtitle (C6) bits in row 25 of the basic page memory are set otherwise TXT5 is used. This allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, TV picture outside) this will be invoked without any further software intervention when such a page is acquired.

Display Modes CC: When attributes superimpose or when boxing (see Table 27, Serial Mode 0/1, bit 6) is set, the resulting display depends on the setting of the following screen control mode bits in REG0:Display Control.

Picture On

Text On

Background On

0

0

x

Text mode, black screen

0

1

0

Text mode, background always black

0

1

1

Text mode

1

0

x

Video mode

1

1

0

Mixed text and TV mode

1

1

1

Text mode, TV picture outside text area

Effect

Table 30 TXT Display Control Bits

2003 Nov 11

83

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications Screen Colour Screen colour is displayed from 10.5 us to 62.5 us after the active edge of the HSync input and on TV lines 23 to 310 inclusive, for a 625 line display, and lines 17 to 260 inclusive for a 525 line display. The screen colour is defined by REG0:Display Control and points to a location in the CLUT table. The screen colour covers the full video width. It is visible when the Full Text or Mixed Screen Colour mode is set and no foreground or background pixels are being displayed.

Display Map The display map allows a flexible allocation of data in the memory to individual rows. Sixteen words are provided in the display memory for this purpose. The lower 10 bits address the first word in the memory where the row data starts. This value is an offset in terms of 16-bit words from the start of Display Memory (8000 Hex). The most significant bit enables the display when not within the scroll (dynamic) area. The display map memory is fixed at the first 16 words in the closed caption display memory. b9

b8

b7

b6

b5

b4

b3

b2

b1

Display possible

Soft Scrolling display possible

Display possible

ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Fig.27 Display Map and Data Pointers SOFT SCROLL ACTION The dynamic scroll region is defined by the REG5:Scroll Area, REG6:Scroll Range, REG14:Top Scroll line and the REG8:Status Register. The scroll area is enabled when the SCON bit is set in REG8: Status. The position of the soft scroll area window is defined using the Soft Scroll Position (SSP max. 18.3 dB treble: 16 kHz -> max. 4.3 dB

$01F

MAIN_SOU_EFF_REG

2003 Nov 11

R/W

BASSFEATURECTRL

[16..14]

$0

DBE, DUB and BBE control $0 = DBE, DUB and BBE Off $1 = DBE main channel On $2 = DUB main channel On $3 = DBE subwoofer channel On $4 = DUB subwoofer channel On $5 = BBE On

-

[23..17]

$0

reserved, must be written as 0

SOMOCTRL

[1..0]

$0

Spatializer sound effect 0 = OFF 1 = I-Stereo 2 = I-Mono 3 = 3D Sound

INSOEF

[4..2]

$3

I-Mono or I-Stereo Effect: Min..Max (6 steps) $0 = 1 (Min) $1 = 2 $2 = 3 $3 = 4 $4 = 5 $5 = 6 (Max)

AVLMOD

[7..5]

$0

AVL mode $0 = OFF $1 = very short decay (20 ms) $2 = short decay (2 sec) $3 = medium decay (4 sec) $4 = long decay (8 sec) $5 = very long decay (16 sec)

AVLWEIGHT

[8]

$1

AVL weighting filter $0 = OFF $1 = ON (recommended)

AVLLEV

[12..9]

$7

AVL reference level (16 steps: -6,-8,... -36 dBFS) $2 = high threshold (-10 dBFS), small reduction ("daytime mode") $7 = medium threshold (-20 dBFS), medium reduction ("evening mode") $C = low threshold (-30 dBFS), strong reduction ("night mode")

174

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

$020

$021

$022

REGISTER

R/W

DBE_COEF_DOWNL_R R/W EG

DUB_COEF_DOWNL_R R/W EG

DOL_CON_REG

R/W

Bitfield Name

Data bits

UOCIII series

Reset value

DETAILLED INFO($= HEX values)

SRS3DCENTE R

[16..13]

$1

SRS 3D Sound Center $0 = -9dB $1 = -14dB $2 = -15dB $3 = -16dB $4 = -17dB $5 = -18dB $6 = -19dB $7 = -20dB $8 = -21dB $9 = -22dB $A = -23dB $B = -24dB $C = -25dB $D = -26dB $E = -27dB $F = off

SRS3DSPACE

[20..17]

$0

SRS 3D Sound Space $0 = -4dB $1 = -5dB $2 = -6dB $3 = -7dB $4 = -8dB $5 = -9dB $6 = -10dB $7 = -11dB $8 = -12dB $9 = -13dB $A = -14dB $B = -15dB $C = -16dB $D = -17dB $E = -18dB $F = off

SRS3DBYPAS S

[21]

$0

SRS 3D Sound bypass mode switch for test purpose $0 = 3D Sound active $1 = Bypass active

-

[23..22]

$0

reserved, must be written as 0

DBEADR

[5..0]

$0

DBE coefficient address

-

[11..6]

$0

reserved, must be written as 0

DBECOEF

[23..12]

$0

DBE coefficients

DUBADR

[7..0]

$0

DUB coefficient address

-

[11..8]

$0

reserved, must be written as 0

DUBCOEF

[23..12]

$0

DUB coefficients

VDSMIXLEV

[2..0]

$0

VDS mix level: 0..100% (5 steps) $0 = 0% $1 = 20% $2 = 40% $3 = 60% $4 = 80% $5 = 100% >$5 = reserved

2003 Nov 11

175

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

REGISTER

R/W

Bitfield Name DPLDEL

Data bits [7..3]

UOCIII series

Reset value $00

DETAILLED INFO($= HEX values) Dolby Prologic : Delayline values: 15..30 ms in 32 steps. $00 = No delay $01 = min. delay $1F = max. delay

2003 Nov 11

BAMAMO

[9..8]

$0

Bass management mode $0 = OFF (Wide Centre Mode) $1 = TYP1 configuration (Normal Centre Mode) $2 = TYP2 configuration (Normal Centre Mode)

BAMASUB

[10]

$0

Bass Management subwoofer filter control $0 = Subwoofer filter Off $1 = Subwoofer filter On

BAMAFC

[14..11]

$0

Bass management lowpass filtercharacteristics: 50 - 400Hz (in 4 Bit resolution)) cornerfrequency. Highpass filter is 1/lowpass. $0 = 50 Hz $1 = 60 Hz $2 = 70 Hz $3 = 80 Hz $4 = 90 Hz $5 = 100 Hz $6 = 110 Hz $7 = 120 Hz $8 = 130 Hz $9 = 140 Hz $A = 150 Hz $B = 200 Hz $C = 250 Hz $D = 300 Hz $E = 350 Hz $F = 400 Hz

FLAT_7KHZ_FI [15] LTER

$0

Dolby Surround ProLogic filter for test purpose $0 = OFF $1 = ON

B_TYPE_FLAT

[16]

$0

Dolby Surround ProLogic filter for test purpose $0 = OFF $1 = ON

ABALCFG

[17]

$1

Dolby Surround ProLogic autobalance for test purpose $0 = OFF $1 = ON

-

[22..18]

$00

reserved, must be written as 0

DelayLineSwitch

[23]

$00

Shift the delay from the DLU to the XMEM $0 = XMEM $1 = DLU

176

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

REGISTER

R/W

Bitfield Name

Data bits

UOCIII series

Reset value

DETAILLED INFO($= HEX values)

SOUND $023

MASTER_VOL_REG

R/W

MASTERVOL

[10..0]

$0

Master volume: (+24..-83.875dB, mute ), controls MAIN, SW, C and S in 1/8dB steps 192 = +24.000 dB 191 = +23.875 dB .. 184 = +23.000 dB .. 0 = 0.000 dB -1 = -0.125 dB .. -671 = -83.875 dB -672 = mute

BEEPVOL

[18..11]

$AC

Beeper volume: (0..-83dB, mute) 0 = 0 dB -1 = -1 dB .. -84 = mute

$024

MAI_VOL_REG

R/W

BEEPFREQ

[21..19]

$0

Beeper frequency: 200..12500 Hz $0 = 200 Hz $1 = 400 Hz $2 = 1000 Hz $3 = 2000 Hz $4 = 3000 Hz $5 = 5000 Hz $6 = 8000 Hz $7 = 12500 Hz

-

[23..22]

$0

reserved, must be written as 0

MAINVOLL

[7..0]

$00

MAIN volume left: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

MAINVOLR

[15..8]

$00

MAIN volume right: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

$025

SW_C_S_VOL_REG

R/W

-

[23..16]

$00

reserved, must be written as 0

SUBWVOL

[7..0]

$0

SUBWOOFER volume: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

2003 Nov 11

177

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

REGISTER

R/W

Bitfield Name CENTERVOL

Data bits [15..8]

UOCIII series

Reset value $0

DETAILLED INFO($= HEX values) CENTER volume: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

SURROUNDVOL

[23..16]

$0

SURROUND volume: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

$026

AUX1_VOL_REG

R/W

AUX1VOLL

[7..0]

$00

AUX1 volume left: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

AUX1VOLR

[15..8]

$00

AUX1 volume rigth: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

$027

AUX2_VOL_REG

R/W

-

[23..16]

$0

reserved, must be written as 0

AUX2VOLL

[7..0]

$00

AUX2 volume left: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

AUX2VOLR

[15..8]

$00

AUX2 volume rigth: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

$028

AUX3_VOL_REG

R/W

-

[23..16]

$0

reserved, must be written as 0

AUX3VOLL

[7..0]

$00

AUX3 volume left: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

AUX3VOLR

[15..8]

$00

AUX3 volume rigth: (+24..-83dB, mute) 24 = +24 dB 23 = +23 dB .. -84 = mute

$029

MAI_TON_CON_REG

R/W

-

[23..16]

$0

reserved, must be written as 0

MAINBASS

[4..0]

$00

MAIN bass: (+15..-16dB, 1 dB steps) 15 = +15 dB .. -16 = -16 dB

2003 Nov 11

178

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

REGISTER

R/W

Bitfield Name MAINTREB

Data bits [9..5]

UOCIII series Reset value $00

DETAILLED INFO($= HEX values) MAIN treble: (+15..-16dB, 1 dB steps) 15 = +15 dB .. -16 = -16 dB

$02A

CENTER_TON_CON_R R/W EG

[23..10]

CENTERBASS [4..0]

$0

reserved, must be written as 0

$0

CENTERbass: (+15..-16dB, 1 dB steps) 15 = +15 dB .. -16 = -16 dB

CENTERTREB [9..5]

$0

CENTERtreble: (+15..-16dB, 1 dB steps) 15 = +15 dB .. -16 = -16 dB

$02B

SUR_TON_CON_REG

R/W

-

[23..10]

$0

reserved, must be written as 0

SURROUNDBASS

[4..0]

$0

SURROUNDbass: (+15..-16dB, 1 dB steps) 15 = +15 dB .. -16 = -16 dB

SURROUNDTREB

[9..5]

$0

SURROUNDtreble: (+15..-16dB, 1 dB steps) 15 = +15 dB .. -16 = -16 dB

$02C

EQMAIN1_TON_CON_ REG

R/W

-

[23..10]

$0

reserved, must be written as 0

EQCHM1

[4..0]

$0

Equalizer MAIN Channel Band 1 (100 Hz) 12 = +12dB .. -12 = -12dB

EQCHM2

[9..5]

$0

Equalizer MAIN Channel Band 2 (300 Hz) 12 = +12dB .. -12 = -12dB

EQCHM3

[14..10]

$0

Equalizer MAIN Channel Band 3 (1000 Hz) 12 = +12dB .. -12 = -12dB

$02D

EQMAIN2_TON_CON_ REG

R/W

-

[23..15]

$0

reserved, must be written as 0

EQCHM4

[4..0]

$0

Equalizer MAIN Channel Band 4 (3000 Hz) 12 = +12dB .. -12 = -12dB

EQCHM5

[9..5]

$0

Equalizer MAIN Channel Band 5 (8000 Hz) 12 = +12dB .. -12 = -12dB

-

2003 Nov 11

[23..10]

$0

reserved, must be written as 0

179

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX $02E

REGISTER

R/W

EQCENTER1_TON_CO R/W N_REG

Bitfield Name EQCHC1

Data bits [4..0]

UOCIII series

Reset value $0

DETAILLED INFO($= HEX values) Equalizer CENTER Channel Band 1 (100 Hz) 12 = +12dB .. -12 = -12dB

EQCHC2

[9..5]

$0

Equalizer CENTER Channel Band 2 (300 Hz) 12 = +12dB .. -12 = -12dB

EQCHC3

[14..10]

$0

Equalizer CENTER Channel Band 3 (1000 Hz) 12 = +12dB .. -12 = -12dB

$02F

EQCENTER2_TON_CO R/W N_REG

-

[23..15]

$0

reserved, must be written as 0

EQCHC4

[4..0]

$0

Equalizer CENTER Channel Band 4 (3000 Hz) 12 = +12dB .. -12 = -12dB

EQCHC5

[9..5]

$0

Equalizer CENTER Channel Band 5 (8000 Hz) 12 = +12dB .. -12 = -12dB

-

[23..10]

$0

reserved, must be written as 0

MON_SRC

[4..0]

$00

source for monitor function $00 = FM,AM,MPX (1 fs) input $01 = FM,AM,MPX (4 fs) input $02 = FM/AM/BTSC/EIAJ DC $03 = FM dematrix output (at DECSEL switch) $04 = NICAM (at DECSEL switch) $05 = MONO (at DECSEL switch) $06 = DEC (at dig. input crossbar) $07 = MONO (at dig. input crossbar) $08 = SAP (at dig. input crossbar) $09 = ADC (at dig. input crossbar) $0A = IIS (at dig. input crossbar) $0B = Noise / silence generator (at dig. input crossbar) $0C = MAIN (at dig. output crossbar) $0D = SUBWOOFER (at dig. output crossbar) $0E = CENTER (at dig. output crossbar) $0F = SURROUND (at dig. output crossbar) $10 = AUX1 (at dig. output crossbar) $11 = AUX2 (at dig. output crossbar) $12 = AUX3 (at dig. output crossbar) $13 = MAIN SUM (at dig. output crossbar) $14 = MAIN (after Bass Management) $15 = SUBWOOFER (after Bass Management) $16 = CENTER (after Bass Management) $17 = SURROUND (after Bass Management)

MONITOR $030

MON_SEL_REG

2003 Nov 11

R/W

180

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

REGISTER

R/W

Bitfield Name

UOCIII series

Reset value

Data bits

DETAILLED INFO($= HEX values)

MON_DET

[6..5]

$3

detection type for monitor function $0 = random samples $1 = absolute value peak detection $2 = quasi peak detection $3 = off / reset peak detector

MON_MAT

[9..7]

$0

matrix for monitor source $0 = A $1 = (A+B)/2 $2 = B $3 = (A-B)/2 (2-ch. sources only)

-

[23..10]

$00

reserved, must be written as 0

I2S_FORMAT

[1..0]

$0

IIS format control $0 = Philips format $1 = Sony format $2 = Japanese 24 bit $3 = Japanese 24 bit

DAC_DWA

[2]

$00

DAC: data weighted averaging $0 = uni-directional, better THD at low levels $1 = bi-directional

-

[23..3]

$00

reserved, must be written as 0

NICLPINV

[0]

1

DCXO scaling control inverter 0 = not inverted 1 = inverted

NICLPSCALE

[3..1]

3

DCXO scaling control gain 0 = 1.0 1 = 0.125 2 = 0.250 3 = 0.375 4 = 0.500 5 = 0.625 6 = 0.750 7 = 0.875

NICLPLIM

[12..4]

511

DCXO scaling control limit (+/- limit), no clipping of control signal if >= 256*scalefactor

GENERAL CONTROL $031

GEN_CTRL_REG

R/W

DEMDEC $032

$033

DCXO_CTRL_REG

R/W

DDEP_OPTIONS1_REG R/W

2003 Nov 11

NICLPCENTER [22..13]

0

DCXO scaling control center

-

[23]

0

reserved, must be written as 0

-

[3..0]

0

reserved, must be written as 0

IDMOD_SLOW [5..4] _EUR

0

in ASD mode, IDMOD setting when European A2 standards (B/G, D/K) are detected 0 = slow 1 = medium 2 = fast

181

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications ABS. ADDR. HEX

REGISTER

R/W

Bitfield Name

UOCIII series Reset value

Data bits

DETAILLED INFO($= HEX values)

IDMOD_SLOW [7..6] _KOR

0

in ASD mode, IDMOD setting when M Korea standard detected 0 = slow 1 = medium 2 = fast

IDMOD_SLOW [9..8] _JAP

1

in ASD mode, IDMOD setting when EIAJ standard detected 0 = slow 1 = medium 2 = fast

-

[18..10]

0

reserved, must be written as 0

SAP_BW

[19]

0

SAP filter bandwidth selection 0 = narrow filter 1 = wide filter

-

[23..20]

0

reserved, must be written as 0

Refresh cycle Minimum refresh cycle period (worst case) can be calculated as follows: Max 42 write registers with 3 datawords each. Each dataword consists of 8 databits + acknowledge bit. If auto increment is applied 1 deviceaddress + 1 subaddress (2 Bytes) is additionally needed. So in total 43* 3 * 9 = 1161 Bits are needed for one transfer. Assuming max. I2C speed (400 kbits/sec) a total time of 1/400k * 1161 = 2.9 msec is needed. So the next transfer cycle (=refresh) cannot start earlier. The following table is an extract of the full address range. Refresh procedure depends on automatic feature (autostandard detection). Table 267 Overview SSD I2C address range wrt. refresh cycle

Address space

Refresh with DDEP mode

Refresh without DDEP

$0001-$0009

Read only

Read only

$000A-$000F

-

Yes

$0010-$0015

Yes

Yes

$0016-$0033

End refresh cycle

End refresh cycle

2003 Nov 11

182

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

VP

supply voltage



5.5

V

VDDA

supply voltage (analogue)

−0.5

3.6

V

VDDP

supply voltage (periphery)

−0.5

3.6

V

VDDC

supply voltage (core)

−0.5

1.95

V

VI

digital inputs

note 1

−0.5

VDD+ 0.5 V

VO

digital outputs

note 1

−0.5

VDD+ 0.5 V

IO

output current (each output)



±10

mA

Tstg

storage temperature

−25

+150

°C

Tamb

operating ambient temperature

0

70

°C

Tsol

soldering temperature



260

°C

Tj

operating junction temperature



150

°C

Ves

electrostatic handling

−2000

+2000

V

+200

V

for 5 s HBM; all pins; notes 2 and 3

MM; all pins; notes 2, 4 and 5 −200 Notes 1. This maximum value has an absolute maximum of 5.5 V independent of VDD. 2. All pins are protected against ESD by means of internal clamping diodes. 3. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF. 4. Machine Model (MM): R = 0 Ω; C = 200 pF.

5. All pins meet this requirement except pin 68 (VSScomb) which can handle a stress voltage of ±150 V. THERMAL CHARACTERISTICS SYMBOL Rth j-a

PARAMETER thermal resistance from junction to ambient in free air (QFP-128)

VALUE tbf

UNIT K/W

QUALITY SPECIFICATION In accordance with “SNW-FQ-611E”. Latch-up At an ambient temperature of 70 °C all pins meet the following specification: • Itrigger ≥ 100 mA or ≥1.5VDD(max) • Itrigger ≤ −100 mA or ≤−0.5VDD(max). Note: The SDA pin (pin 109 of the “standard version” or pin 20 of the “face down version) does not meet this specification and has a maximum trigger current of −20 mA. For the positive current it meets the requirement of 100 mA.

2003 Nov 11

183

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

CHARACTERISTICS OF MICRO-COMPUTER AND TEXT DECODER VDD = 3.3 V ± 10%; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified NUMBER

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies VM.1.1

supply voltage (VDDA)

3.0

3.3

3.6

V

VM.1.2

supply voltage (VDDP)

3.0

3.3

3.6

V

VM.1.3

supply voltage (VDDC)

1.65

1.8

1.95

V

VM.1.4

periphery supply current (IDDP)

note 1

1





mA

VM.1.5

core supply current (IDDC)

normal mode



440

tbf

mA

VM.1.6

supply current IDDA + IDDP

normal mode



28

tbf

mA

VM.1.7

supply current IDDA + IDDP

stand-by mode



15

tbf

mA

VM.1.8

supply current IDDA + IDDP

idle mode



9

tbf

mA

VM.1.9

supply current IDDA + IDDP

power down mode



7.5

tbf

mA

Digital input/outputs P0.0 TO P0.5, P1.0 TO P1.5, P2.0 TO P2.5 AND P3.0 TO P3.3 IO.1.1

low level input voltage





0.8

V

IO.1.2

high level input voltage

2





V

IO.1.3

hysteresis of Schmitt Trigger input

0.4





V

IO.1.4

low level output voltage

IOL = 4 mA





0.4

V

IO.1.5

high level output voltage

open drain





3.3

V

IO.1.6

high level output voltage

IOH = 4 mA; push pull

VDDE − 0.4





V

IO.1.7

output rise time (push-pull only) 10% to 90%

load 40 pF



5



ns

IO.1.8

output fall time 10% to 90%

load 40 pF



5



ns

IO.1.9

load capacitance





100

pF

IO.1.10

capacitance of input pin





1

pF

2003 Nov 11

184

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

P1.6 AND P1.7 (OPEN DRAIN) IO.2.1

low level input voltage (VIL)





0.8

V

IO.2.2

high level input voltage (VIH)

2





V

IO.2.3

hysteresis of Schmitt-trigger input

0.4





V

IO.2.4

low level output voltage





0.4

V

IO.2.5

high level output voltage





3.3

V

IO.2.6

output fall time 10% to 90%

P1.6; load 160 pF



180



ns

IO.2.7

output fall time 10% to 90%

P1.7; load 400 pF



140



ns

IO.2.8

bus load capacitance





400

pF

IO.2.9

capacitance of IO pin





1

pF

sink current 4 mA

Crystal oscillator OSCIN; NOTE

2

X.1.1

resonator frequency



24.576



MHz

X.1.2

input capacitance (Ci)



tbf



pF

X.1.3

output capacitance (Co)



tbf



pF

X.1.4

Ri (crystal)





100



X1.5

maximum load capacitance





25

pF

Cx1 or Cx2 in Fig 52

Note 1. Peripheral current is dependent on external components and voltage levels on I/Os 2. The simplified circuit diagram of the oscillator is given in Fig.52. A suitable crystal for this oscillator is the Saronix type 9922 520 20264.

2003 Nov 11

185

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

CHARACTERISTICS OF STEREO DECODER AND DIGITAL AUDIO PROCESSOR VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note tbn; VDD1,2,3 = 3.3 V;VDDA5 = 5.0 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with EBU specification; 1 kΩ measurement source resistance for AF inputs; unless otherwise specified; SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies VSSC4 VDDC4 VDDA3 VDDA GNDA VDDA2 VDDC2 VSSC2 VDDC3 VSSC3

digital supply ground for Audio-DAC digital supply voltage for Audio-DAC analogue supply voltage for Audio-DAC analogue supply voltage for Audio-ADC analogue supply ground for Audio-ADC analogue supply voltage for Audio-ADC digital supply voltage for SIF-ADC digital supply ground for SIF-ADC digital supply voltage for Audio-ADC digital supply ground for Audio-ADC

-

0.0

-

V

1.65

1.8

1.95

V

VREF_POS

3.3

3.6

V

-0.25 1.6

1.8

2.0

V

-

0.0

-

V

3.0

3.3

3.6

V

1.6

1.8

2.0

V

-

0.0

-

V

1.6

1.8

2.0

V

-

0.0

-

V

positive analog reference voltage for SDAC “LSL” negative analog reference voltage for SDAC “LSL+LSR” positive analog reference voltage for SDAC “LSR+HPL” negative analog reference voltage for SDAC “HPL+HPR” positive analog reference voltage for SDAC “HPR” positive analog reference voltage for Audio-ADC negative analog reference voltage for Audio-ADC analog reference voltage for Audio-ADC

0.8

3.3

3.6

V

-

0.0

-

V

0.8

3.3

3.6

V

-

0.0

-

V

0.8

3.3

3.6

V

3.0

3.3

3.6

V

-

0.0

-

V

References VREF_POS _LSL VREF_NEG _LSL+LSR VREF_POS _LSR+HPL VREF_NEG _HPL+HPR VREF_POS _HPR VREFAD _POS VREFAD _NEG VREFAD

2003 Nov 11

VDDA2/2

186

CONFIDENTIAL

V

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications SYMBOL

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Demodulator performance; THD + N

S/N

B−3

total harmonic distortion plus noise

signal-to-noise ratio

−3 dB bandwidth

FR

frequency response 20 Hz to 14 kHz

αcs(dual) αcs(stereo) αAM

dual signal channel separation stereo channel separation AM suppression for FM

S/NAM

AM demodulation

from FM source to any output; Vo = 1 V (rms) with low-pass filter from NICAM source to any output; Vo = 1 V (rms) with low-pass filter SC1 from FM source to any output; Vo = 1 V (rms); CCIR468; quasi peak SC2 from FM source to any output; Vo = 1 V (rms); CCIR468; quasi peak NICAM source; Vo = 1 V (rms) from FM source to any output from NICAM source to any output from FM or NICAM to any output; fref = 1 kHz; inclusive pre-emphasis and de-emphasis



0.35

0.5

%



0.1

0.3

%

64

70



dB

60

66



dB

NICAM in accordance with EBU specification; note tbn 14.5 15 −

kHz

14.5

15



kHz



±2



dB

65 40 50

70 45 −

− − −

dB dB dB

45



dB

25

50

75

%



27



dBc ---------Hz

116.85 116.11 114.65

− − −

118.12 118.89 120.46

Hz Hz Hz

273.44 272.07 270.73

− − −

274.81 276.20 277.60

Hz Hz Hz

AM: 1 kHz, 30% modulation; reference: 1 kHz, 50 kHz deviation 2ndSIF level 100 mV (rms); 36 54% AM; 1 kHz AF; CCIR468; quasi peak

IDENTIFICATION FOR FM SYSTEMS modp C/Np fident

2003 Nov 11

pilot modulation for identification pilot sideband C/N for identification start identification window

B/G stereo slow mode medium mode fast mode B/G dual slow mode medium mode fast mode

187

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications SYMBOL tident

PARAMETER total identification time ON or OFF

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

slow mode medium mode fast mode

− − −

− − −

2 1 0.5

s s s

output voltage at 0dBFS; Vo = 1.0 V (rms); fi = 1 kHz; bandwidth 20 Hz to 14 kHz; output reference level Vo = 1.0 V (rms); fi = 1 kHz; CCIR468; RMS; from I2S to D/A; between any analog audio signal pairs; fi = 1 kHz between left and right of any analog audio signal pair



0.1

0.3

%

-

80



dB

70





dB

65





dB

Audio performance (D/A) THD + N

total harmonic distortion plus noise

S/N

signal-to-noise ratio

αct

crosstalk attenuation

αcs

channel separation

2003 Nov 11

188

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

CHARACTERISTICS OF TV-PROCESSOR VP = 5 V; Tamb = 25 °C; unless otherwise specified. NUMBER

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies MAIN SUPPLY; NOTE 1 V.1.1

main supply voltage

V.1.2

digital supply voltage

V.1.3

audio supply voltage

note 2 note 3

4.7

5.0

5.3

V

3.0

3.3

3.6

V

4.7

8.0

8.4

V

V.1.4

main supply current (5 V)



190



mA

V.1.5

digital supply current (3.3 V)



8



mA

V.1.6

audio supply current (5.0/8.0 V)



0.5



mA

V.1.7

total power dissipation



980



mW

IF circuit VISION IF AMPLIFIER INPUTS input sensitivity (RMS value)

note 4

M.1.1

fi = 38.90 MHz



75

150

µV

M.1.2

fi = 45.75 MHz



75

150

µV

M.1.3

fi = 58.75 MHz



75

150

µV

input resistance (differential)

note 5



2



kΩ

note 5

M.1.4 M.1.5

input capacitance (differential)



3



pF

M.1.6

gain control range

64





dB

M.1.7

maximum input signal (RMS value)

150





mV

PLL DEMODULATOR; NOTES 6 AND 7 M.2.1

Free-running frequency of VCO

PLL not locked, deviation from nominal setting

−500



+500

kHz

M.2.2

Catching range PLL

without SAW filter



±1



MHz

M.2.3

delay time of identification

via LOCK bit





20

ms

VIDEO AMPLIFIER OUTPUT (IFOUT); NOTE 8 M.3.1

zero signal output level

M.3.2

negative modulation; note 9



3.6



V

positive modulation; note 9



1.4



V

M.3.3

top sync level

negative modulation

1.3

1.4

1.5

V

M.3.4

white level

positive modulation



3.4



V

M.3.5

difference in amplitude between negative and positive modulation



0

15

%

M.3.6

video output impedance



50





M.3.7

internal bias current of NPN emitter follower output transistor

1.0





mA





5

mA

6

7



MHz

M.3.8

maximum source current

M.3.9

bandwidth of demodulated output signal

2003 Nov 11

at −3 dB

189

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VIDEO AMPLIFIER (CONTINUED) M.3.10

differential gain

note 10



2

5

%

M.3.11

differential phase

notes 10 and 11





5

deg

M.3.12

video non-linearity

note 12





5

%

M.3.13

white spot clamp level



3.8



V

M.3.14

noise inverter clamping level

note 13



1.2



V

M.3.15

noise inverter insertion level (identical to black level)

note 13



2.3



V

intermodulation

notes 11 and 14 Vo = 0.92 or 1.1 MHz

60

66



dB

Vo = 2.66 or 3.3 MHz

60

66



dB

Vo = 0.92 or 1.1 MHz

56

62



dB

Vo = 2.66 or 3.3 MHz

60

66



dB

M.3.16

blue

M.3.17 M.3.18

yellow

M.3.19 signal-to-noise ratio

notes 11 and 15

M.3.20

weighted

56

60



dB

M.3.21

unweighted

49

53



dB

M.3.22

residual carrier signal

note 11



5.5



mV

M.3.23

residual 2nd harmonic of carrier note 11 signal



2.5



mV



V

VIDEO OUTPUT/INPUT (IFVO/SVO/CVBSI), CONTROLLED BY THE SVO1/SVO0 BITS; SEE NOTE 16 M.3.24

output signal amplitude (peak-to-peak value)

SVO1/SVO0 = 0/0 or 0/1



2.0

M.3.25

top sync level

SVO1/SVO0 = 0/0 or 0/1



0.5



V

M.3.26

output impedance

SVO1/SVO0 = 0/0 or 0/1





50



M.3.27

CVBS input voltage (peak-to-peak value)

SVO1/SVO0 = 1/0



1.0

1.4

V

M.3.28

input current

SVO1/SVO0 = 1/0



2



µA

GROUP DELAY CORRECTION, SEE FIGURES 63 AND 64; NOTE 17 M.3.29

group delay sound trap only

at f=4.43MHz; sound trap frequency 5.5 MHz



180



ns

M.3.30

group delay sound trap plus group delay correction filter

at f=4.43MHz; sound trap frequency 5.5 MHz



170



ns

-3 dB video bandwidth (sound trap + group delay)

fSC1=4.5MHz

3.90

4.00



MHz

fSC1=5.5MHz

4.80

4.90



MHz

fSC1=6.0MHz

5.25

5.35



MHz

SOUND TRAP M.3.31

fSC1=6.5MHz M.3.32

2003 Nov 11

Attenuation at first sound carrier 4.5 and 5.5MHz fSC1 6.0 and 6.5MHz

190

CONFIDENTIAL

5.70

5.80



MHz

30

36



dB

26

32



dB

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SOUND TRAP (CONTINUED) M.3.33

Attenuation at second sound carrier fSC2

f=4.726Mhz; fSC1=4.5MHz

21

27



dB

f=5.742MHz; fSC1=5.5MHz

21

27



dB

f=6.55Mhz; fSC1=6.0MHz

12

18



dB

18

24



dB

amplitude response at the colour f=3.58 MHz; fSC1=4.5 MHz subcarrier frequency f=4.43 MHz; fSC1=5.5 MHz



1.0

2.0

dB



1.0

2.0

dB

f=4.43 MHz; fSC1=6.0 MHz



1.0

2.0

dB

f=4.28 MHz; fSC1=6.5 MHz



1.0

2.0

dB

f=6.742MHz; fSC1=6.5MHz M.3.34

IF AND TUNER AGC; NOTE 18

Timing of IF-AGC M.4.1

modulated video interference

30% AM for 1 mV to 100 mV; − 0 to 200 Hz (system B/G)



10

%

M.4.2

response time to IF input signal amplitude increase of 52 dB

positive and negative modulation



2



ms

M.4.3

response to an IF input signal amplitude decrease of 52 dB

negative modulation



50



ms

positive modulation



100



ms

M.4.4

Tuner take-over adjustment (via

I2C-bus)

M.5.1

minimum starting level for tuner take-over (RMS value)



0.4

0.8

mV

M.5.2

maximum starting level for tuner take-over (RMS value)

50

150



mV





5

V

Tuner control output M.6.1

max. tuner AGC output voltage

maximum tuner gain; note 5

M.6.2

output saturation voltage

minimum tuner gain; IO=2 mA −



300

mV

M.6.3

maximum tuner AGC output swing

1.0





mA

M.6.4

leakage current RF AGC





1

µA

M.6.5

input signal variation for complete tuner control

0.5

2

4

dB

AFC OUTPUT (VIA I2C-BUS); NOTE 19 M.7.1

AFC resolution



2



bits

M.7.2

window sensitivity



125



kHz

M.7.3

window sensitivity in large window mode



275



kHz





10

ms

VIDEO IDENTIFICATION OUTPUT (VIA IFI BIT IN OUTPUT BYTE 00) M.8.1

2003 Nov 11

delay time of identification after the AGC has stabilized on a new transmitter

191

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DVB IF, note 20 DVB IF AMPLIFIER INPUTS VS.1.1

input sensitivity (RMS value)

fi = 36/44 MHz



75

150

µV

VS.1.2

input resistance (differential)

note 5



2



kΩ

VS.1.3

input capacitance (differential)

note 5



3



pF

VS.1.4

gain control range

64





dB

VS.1.5

maximum input signal (RMS value)

150





mV



43.008



MHz

I-MIXER, NOTE 21 VS.2.1

oscillator frequency; note

OFDM application



49.152



MHz

VS.2.2

maximum oscillator phase noise

−106





dB

VS.2.5

lower limit passband





1.0

MHz

VS.2.11

VSB application

VS.2.6

upper limit passband

7.0





MHz

VS.2.7

passband ripple





0.5

dB

VS.2.8

stopband



29



MHz

VS.2.9

stopband attenuation

40





dB

EXTERNAL AGC CONTROL VS.3.1

voltage range for full control of the amplifier

1



3

V

VS.3.2

input impedance

1





MΩ

MIXED DOWN OUTPUT SIGNAL VS.4.1

output voltage (peak-to-peak value)



1



V

VS.4.2

output impedance



25





VS.4.3

dc output level



2.0



V

QSS Sound IF circuit SOUND IF AMPLIFIER −3 dB

Q.1.1

input sensitivity (RMS value)

Q.1.3

maximum input signal

Q.1.5

input resistance (differential)

note 5 note 5



45

tbf

dBµV

tbf

100



dBµV



2



kΩ

Q.1.6

input capacitance (differential)



3



pF

Q.1.7

gain control range



55



dB

Q.1.8

crosstalk attenuation between SIF and VIF input

50





dB

2003 Nov 11

192

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SOUND IF INTERCARRIER OUTPUT; WITH AM = 0 Q.2.1

output signal amplitude (RMS value)

Q.2.2

75

100

125

mV

bandwidth (-3 dB)

7.5

10



MHz

Q.2.3

residual IF sound carrier (RMS value)



2



mV

Q.2.4

output resistance



300





Q.2.5

DC output voltage



2.0



V

Q.2.6

internal bias current of emitter follower



1.0



mA

Q.2.7

maximum AC and DC sink current



1.0



mA

Q.2.8

maximum AC and DC source current



1.0



mA

Q.2.9

weighted S/N ratio (SC1/SC2). black picture Ratio of PC/SC1 at vision IF white picture input of 40 dB or higher, note 22 6 kHz sinewave (black-to-white modulation)

Q.2.10 Q.2.11

SC-1; sound carrier 2 off

53/48

58/55



dB

52/47

55/53



dB

44/42

48/46



dB

Q.2.12

250 kHz sine wave (black-to-white modulation)

44/25

48/30



dB

Q.2.13

sound carrier subharmonics (f=2.75 MHz ± 3 kHz)

45/44

51/50



dB

Q.2.14

sound carrier subharmonics (f=2.87 MHz ± 3 kHz)

46/45

52/51



dB

AM SOUND OUTPUT; DEPENDING ON SETTING OF CMB0/CMB1 AND AM BITS Q.3.1

AF output signal amplitude (RMS value)

54% modulation

200

250

300

mV

Q.3.2

total harmonic distortion

54% modulation



1.0

2.0

%

Q.3.21

total harmonic distortion

80% modulation



2.0

5.0

%

Q.3.3

AF bandwidth

−3 dB

100

125



kHz

Q.3.4

weighted signal-to-noise ratio

54% modulation, weighted with CCIR-1k filter, RMS SIF level @ 80 dBµV



45



dB

Q.3.5

DC output voltage



2.5



V

Q.3.6

power supply ripple rejection



20



dB

17



300

mVRMS

2nd Sound IF AGC circuit 2ND SOUND IF EXTERNAL INPUT, NOTE 23 Q.4.1

input voltage range

Q.4.2

input frequency range

note 24

4.5



10.7

MHz

Q.4.3

input resistance

note 5



25



kΩ

Q.4.4

input capacitance

note 5



3



pF

2003 Nov 11

193

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2ND SOUND IF AGC Q.5.1

gain control range



24



dB

Q.5.2

charge current AGC pin

FM mode





12.5

µA

Q.5.3

discharge current AGC pin

FM mode





50

µA

Q.5.4

charge current AGC pin

AM mode





2.5

µA

Q.5.5

discharge current AGC pin

AM mode





2.5

µA

Q.5.6

discharge current AGC pin

overload condition



1



mA

26

30



dB

40

46



dB



1

2

mV

FM demodulator and audio pre-amplifier FM-PLL DEMODULATOR G.1.2

gain control range AGC amplifier

G.1.7

AM rejection

note 25

EXTERNAL SOUND IF INPUT (SSIF, WHEN SELECTED) G.1.8

input limiting for lock-in of PLL (RMS value)

G.1.9

input resistance

note 5



50



kΩ

G.1.10

input capacitance

note 5





1.0

pF

notes 26 and 27



125



mV

DE-EMPHASIS OUTPUT G.2.1

output signal amplitude (RMS value)

G.2.2

output resistance



15



kΩ

G.2.3

DC output voltage



2.5



V

G.2.31

signal-to-noise ratio (RMS value) note 28



50



dB



125



mV

AUDIO INPUT VIA DEEMPHASIS OUTPUT; NOTE 29 G.2.4

input signal amplitude (RMS value)

G.2.5

input resistance



15



kΩ

G.2.6

voltage gain between input and output



−3



dB



1.0

1.3

Vrms

Audio Selectors and Volume control EXTERNAL AUDIO INPUTS; NOTE 30 A.1.1 A.1.11

maximum input voltage (RMS value)

A.1.2

input resistance

A.1.3

gain from audio inputs to fixed audio outputs (stereo versions)

A.1.41

5V audio supply



1.0

1.4

Vrms

24

32



kΩ

DSG = 0



0



dB

DSG = 1



6



dB

gain from audio inputs to AUDOUT output at maximum volume (mono versions)

DSG = 0



6



dB

DSG = 1



12



dB

A.1.5

crosstalk between channels

5 V audio supply



tbf



dB

A.1.6

crosstalk between left and right

5 V audio supply



tbf



dB

A.1.31 A.1.4

2003 Nov 11

8V audio supply

194

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

FIXED AUDIO OUTPUTS (STEREO AND AV STEREO VERSIONS) A.2.1 A.2.2

maximum output signal amplitude (RMS value)

A.2.3

output impedance

A.2.4

total harmonic distortion

A.2.5 A.2.6

signal-to-noise ratio

A.2.7

frequency range

5V audio supply

1.0





Vrms

8V audio supply

2.0





Vrms



500

650



at +6 dBV



tbf



dB

at -54 dBV; A-weighted



tbf



dB

referred to +6dBV output level; A-weighted



tbf



dB

20



15.000

Hz

5 V audio supply; note 31

250

350

450

mV

8 V audio supply; note 31

500

700

900

mV



500







2.2



V

ANALOGUE VOLUME CONTROLLED AUDIO OUTPUT(S) A.3.1 A.3.11

controlled output signal amplitude (RMS value)

A.3.2

output resistance

A.3.3

DC output voltage

5 V audio supply 8 V audio supply



3.3



V

A.3.4

total harmonic distortion

note 32





0.5

%

A.3.5

power supply rejection

note 11



20



dB

A.3.31

A.3.6

internal signal-to-noise ratio

note 11 + 28 + 33



50



dB

A.3.7

external signal-to-noise ratio

note 11 + 33



60



dB

A.3.8

control range

see also Fig.53



70



dB

A.3.9

suppression of output signal when mute is active



70



dB

A.3.10

DC shift output during muting



10

50

mV

ANALOGUE AUTOMATIC VOLUME LEVELLING; NOTE 34 A.4.1

gain at maximum boost



+6



dB

A.4.2

gain at minimum boost



-14



dB

A.4.3

charge (attack) current



1



mA

A.4.4

discharge (decay) current



200



nA

A.4.5

control voltage at maximum boost



1



V

A.4.6

control voltage at minimum boost



3



V

2003 Nov 11

195

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CVBS, Y/C and RGB/YUV/YPRPB INPUTS CVBS-Y/C SWITCH −

1.0

1.4

V



2



µA

50





dB

chrominance input voltage (burst note 5 and 37 amplitude)



0.3

1.0

V

chrominance input impedance



50



kΩ



2.0



V

S.1.1

CVBS or Y input voltage (peak-to-peak value)

S.1.2

CVBS or Y input current

S.1.3

suppression of non-selected CVBS input signal

S.1.4 S.1.5

note 35

notes 11 and 36

CVBS OUTPUT ON CVBSO S.1.9

output signal amplitude (peak-to-peak value)

S.1.10

top sync level



0.5



V

S.1.11

output impedance





50



EXTERNAL RGB / YUV / YPBPR INPUT S.2.1

RGB input signal amplitude for an output signal of 1.2 V (black-to-white) (peak-to-peak value)

note 38



0.7

0.8

V

S.2.2

RGB input signal amplitude before clipping occurs (peak-to-peak value)

note 11

1.0





V

S.2.3

Y input signal amplitude (peak-to-peak value)

1.4/1.0

2.0

V

S.2.4

U/PB input signal amplitude (peak-to-peak value)

−1.33/ +0.7

2.0

V

S.2.5

V/PR input signal amplitude (peak-to-peak value)

input signal amplitude for an − output signal of 1.2 V (black-to-white); when − activated via the YUV2-YUV0 bits; note 39 −

−1.05/ +0.7

1.5

V

S.2.6

difference between black level of internal and external signals at the outputs





20

mV

S.2.7

input currents

no clamping; note 5



0.1

1

µA

S.2.8

delay difference for the three channels

note 11



0

20

ns

63 steps; see Fig.56



±30



deg

BASE-BAND TINT CONTROL S2.9

2003 Nov 11

tint control range

196

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

FAST INSERTION S.3.1

input voltage

S.3.2

no insertion





0.4

V

insertion

0.9





V

S.3.3

maximum input pulse

insertion





5.0

V

S.3.4

delay time from RGB in to RGB out

insertion; note 11





20

ns

S.3.5

delay difference between insertion; note 11 insertion to RGB out and RGB in to RGB out





20

ns

S.3.6

input impedance



500



kΩ

S.3.7

suppression of internal RGB signals

notes 11 and 36; insertion; fi = 0 to 5 MHz



55



dB

S.3.8

suppression of external RGB signals

notes 11 and 36; no insertion; fi = 0 to 5 MHz



55



dB

YUV INTERFACE (COLOUR DIFFERENCE OUTPUT AND INPUT SIGNALS); NOTE 40 S.4.1

signal amplitude (R−Y) (peak-to-peak value)

INTF = 1, note 5

0.94

1.05

1.16

V

S.4.2

signal amplitude (B−Y) (peak-to-peak value)

INTF = 1, note 5

1.19

1.33

1.47

V

S.4.3

signal amplitude (PR) (peak-to-peak value)

INTF = 0, note 5

0.63

0.7

0.77

V

S.4.4

signal amplitude (PB) (peak-to-peak value)

INTF = 0, note 5

0.63

0.7

0.77

V

S.4.5

output impedance



500





YUV INTERFACE (LUMINANCE OUTPUT AND INPUT SIGNAL); NOTE 40 S.5.1

output signal amplitude (peak-to-peak value)

top sync-white, INTF=0

tbf

1.0

tbf

V

S.5.2

output signal amplitude (peak-to-peak value)

top sync-white, INTF=1

tbf

1.4

tbf

V

S.5.3

top sync level

INTF=0



1.5



V

S.5.4

top sync level

INTF=1



1.4



V

S.5.5

output impedance

INTF=0



250





S.5.6

output impedance

INTF=1



250





2003 Nov 11

197

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

PAL / NTSC Comb Filter LUMINANCE SIGNAL F.1.1

luminance gain error

F.1.2

-3 dB luminance bandwidth

−1

0

+1

dB

COMB mode, fSC = 4.43 MHz 6





MHz

F.1.3

COMB mode, fSC = 3.58 MHz 5





MHz

F.1.4

YC mode, fSC = 4.43 MHz

6





MHz

YC mode, fSC = 3.58 MHz

5





MHz

f = 4 x fSC





−30

dB

F.1.7

f = 2 x fSC





−30

dB

F.1.8

f = 1.33 x fSC





−30

dB

F.1.9

f = fSC





−40

dB

26





dB

suppression (comb depth) with fSC = 4.43 MHz; see Fig.70 respect to luminance band pass f = fSC 30 nearest to fSC f = ((283.75-74)/283.75)x fSC −





dB

10



dB

10



dB





dB

F.1.5 F.1.6

F.1.10

F.1.11 F.1.12

residues of clock frequencies in the luminance signal (Vrms/1V)

COMB mode

cross talk suppression at vertical see note 41, vertical transient black ↔ multi-burst transition active video ↔ (1V/V (p-p)) vertical blanking, see the figures 68 and 69.

f = ((283.75+74)/283.75)x fSC −

F.1.13

PAL-M; see Fig.70 F.1.14

f = fSC

30

F.1.15

f = ((227.25-59)/227.25)x fSC −

10



dB

F.1.16

f = ((227.25+59)/227.25)x fSC −

10



dB

PAL N; see Fig.70 F.1.17

f = fSC





dB

F.1.18

f = ((229.25-59)/229.25)x fSC −

10



dB

F.1.19

f = ((229.25+59)/229.25)x fSC −

10



dB

30

NTSC M, see Fig.70 F.1.20

f = fSC

30





dB

F.1.21

f = ((227.5-59)/227.5) x fSC



10



dB

F.1.22

f = ((227.5+59)/227.5) x fSC



10



dB

30





dB

NTSC 4.4 MHz, see Fig.70 F.1.23

f = fSC

F.1.24

f = ((281.75-74)/281.75) x fSC −

10



dB

F.1.25

f = ((281.75+74)/281.75) x fSC −

10



dB



+150

ns

Y DELAY ADJUSTMENT (VALID FOR PAL, NTSC AND SECAM) F.1.26

2003 Nov 11

tuning range delay time

8 steps; note 42

198

CONFIDENTIAL

−150

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CHROMINANCE SIGNAL F.2.1

chrominance gain error

−1

0

+1

dB

F.2.2

-3 dB chrominance bandwidth

COMB mode, around fSC,

1.5





MHz

F.2.3

chrominance signal-to-noise ratio (0.7V/Vrms noise)

unweighted; fSC±0.3fSC

56





dB

residues of clock frequencies in the chrominance signal (Vrms/0.7V)

COMB mode f = 4 x fSC





−30

dB

f = 2 x fSC





−30

dB

F.2.6

f = 1.33 x fSC





−40

dB

F.2.7

f = fSC





−50

dB

26





dB

f = (284/283.75) x fSC

30





dB

f = ((284-74)/283.75) x fSC

30





dB

f = ((284+74)/283.75) x fSC

30





dB

F.2.4 F.2.5

F.2.8

F.2.9 F.2.10 F.2.11

cross talk suppression at vertical see note 43, vertical transient no-colour ↔ colour transition active video ↔ (0.7V/V (p-p)) vertical blanking, see the figures 68 and 69 suppression (comb depth) with respect to chrominance band pass at f = fSC

fSC = 4,43 MHz; see Fig.71

PAL M, see Fig.71 F.2.12

f = (227/227.25) x fSC

30





dB

F.2.13

f = ((227-59)/227.25) x fSC

30





dB

F.2.14

f = ((227+59)/227.25) x fSC

30





dB

PAL N, see Fig.71 F.2.15

f = (229/229.25) x fSC

30





dB

F.2.16

f = ((229-59)/229.25) x fSC

30





dB

F.2.17

f = ((229+59)/229.25) x fSC

30





dB

NTSC M, see Fig.71 F.2.18

f = (227/227.5) x fSC

30





dB

F.2.19

f = ((227-59)/227.5) x fSC

30





dB

F.2.20

f = ((227+59)/227.5) x fSC

30





dB

NTSC 4.4 MHz, see Fig.71 F.2.21

f = (282/281.75) x fSC

30





dB

F.2.22

f = ((282-74)/281.75) x fSC

30





dB

F.2.23

f = ((282+74)/281.75) x fSC

30





dB

2003 Nov 11

199

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Chrominance and Luminance filters CHROMINANCE TRAP CIRCUIT; NOTE 44 −

fsc



MHz

−3 dB



2.7



MHz

−3 dB



3.3



MHz

colour subcarrier rejection

24

26



dB

trap frequency during SECAM reception



4.3



MHz



MHz MHz

F.3.1

trap frequency

F.3.2

Bandwidth at fSC = 3.58 MHz

F.3.3

Bandwidth at fSC = 4.43 MHz

F.3.4 F.3.5

CHROMINANCE BANDPASS CIRCUIT F.4.1

centre frequency (CB = 0)



fsc

F.4.2

centre frequency (CB = 1)



1.1×fsc



F.4.3

bandpass quality factor



3



4.26

4.29

4.31

MHz

241

268

295

kHz

CLOCHE FILTER F.5.1

centre frequency

F.5.2

Bandwidth

CLO = 0

Picture Improvement Features PEAKING CONTROL; NOTE 45 P.1.1

width of preshoot or overshoot

P.1.2

peaking signal compression threshold

P.1.3

overshoot at maximum peaking

P.1.4

setting PF1/PF0 = 0/0



190



ns

setting PF1/PF0 = 0/1



160



ns

setting PF1/PF0 = 1/0



143



ns

setting PF1/PF0 = 1/1



125



ns



50



IRE

positive, direction “white”



45



%

negative



75



%



1.7



P.1.5

Ratio negative/positive overshoot; note 46

P.1.6

peaking control curve

63 steps

see Fig.54

P.1.7

peaking centre frequency

setting PF1/PF0 = 0/0



2.7



MHz

P.1.8

setting PF1/PF0 = 0/1



3.1



MHz

P.1.9

setting PF1/PF0 = 1/0



3.5



MHz

P.1.10

setting PF1/PF0 = 1/1



4.0



MHz



10



IRE

CORING STAGE; NOTE 47 P.1.10

2003 Nov 11

coring range

200

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

BLACK LEVEL STRETCHER; NOTE 48 P.2.1

Maximum black level shift

BSD = 0

25

30

35

IRE

P.2.11

Maximum black level shift

BSD = 1

10

15

20

IRE

P.2.2

level shift at 100% peak white

−1

0

1

IRE

P.2.3

level shift at 50% peak white

−1



3

IRE

P.2.4

level shift at 15% peak white

BSD = 0

10

12

14

IRE

P.2.5

level shift at 15% peak white

BSD = 1

4

6

8

IRE

DYNAMIC SKIN TONE (FLESH) CONTROL; NOTE 49 P.4.1

control angle



123



deg

P.4.32

correction range (angle)



45



deg

40

50

60

%

GAMMA CONTROL; NOTE 50 P.6.1

break point of characteristic

maximum white is 100%

P.6.2

maximum expansion

set by the bits WS1/WS0

6

8

12

%

P.6.3

mismatch for YIN = 100 IRE

at maximum expansion

−2



+8

IRE

P.6.4

mismatch for YIN = 0 IRE

at maximum expansion

−2



+4

IRE

BLUE STRETCH; NOTE 51 P.7.1

increase of small signal gain for the blue channel

BLS = 1



20



%

P.7.2

decrease of small signal gain for BLS = 1 the red channel



20



%



10



IRE



1.5



V

DC TRANSFER RATIO OF LUMINANCE SIGNAL; NOTE 52 P.8.1

reduction of black level for white TFR = 1 picture (100 IRE)

SCAN VELOCITY MODULATION OUTPUT; NOTES 53 AND 54 P.9.1

output signal amplitude (peak-to-peak value

VMA1/VMA0 = 1/1

P.9.11

output signal amplitude (peak-to-peak value

VMA1/VMA0 = 1/1



1.8



V

P.9.2

delay of RGB output signal with respect to SVM output

SVM2-SVM0 = 000, PF1-PF0 − = 01 (peaking frequency of 3.1 MHz) and 50% input signal amplitude

170



ns

P.9.3

coring range

CRA0 = 0



8



%

P.9.4

maximum DC-current through the SVM output

VMA1/VMA0 = 0/0



100



µA

2003 Nov 11

SMD1/SMD0 = 0/1

SMD1/SMD0 = 1/0

201

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Horizontal and vertical synchronization and drive circuits SYNC VIDEO INPUT H.1.1

sync pulse amplitude

note 5

50

300

350

mV

H.1.2

slicing level for horizontal sync

note 55



45



%

H.1.3

slicing level for vertical sync

note 55



35



%

HORIZONTAL OSCILLATOR H.2.1

free running frequency



15625



Hz

H.2.2

spread free running frequency





±2

%

H.2.3

frequency variation with respect VP = 8.0 V ±10%; note 11 to the supply voltage



0.2

0.5

%

H.2.4

frequency variation with temperature

Tamb = 0 to 70 °C; note 11





80

Hz



±0.8

±1.1

kHz

±0.5

±0.8



kHz

FIRST CONTROL LOOP; NOTE 56 H.3.1

holding range PLL

H.3.2

catching range PLL

H.3.3

S/N ratio video input signal to switch the time constant



24



dB

H.3.4

hysteresis at the switching point



3



dB

note 11

SECOND CONTROL LOOP H.4.1

control sensitivity



150



µs/µs

H.4.2

control range from start of horizontal output to flyback at nominal shift position



19



µs

H.4.3

horizontal shift range

±2





µs

H.4.4

control sensitivity for dynamic compensation



13



µs/V

H.4.5

Voltage to switch-on the ‘flash’ protection

4.0





V

H.4.6

Input current during protection





1

mA

H.4.7

control range parallelogram correction

note 58



±0.75



µs

H.4.8

control range bow correction

note 58



±1.0



µs

63 steps

note 57

HORIZONTAL OUTPUT; NOTE 59 H.5.1

LOW level output voltage





0.3

V

H.5.2

maximum allowed output current

10





mA

H.5.3

maximum allowed output voltage





VP

V

H.5.4

duty factor

VOUT = LOW (TON); SDC = 0 −

55



%

H.5.41

duty factor

VOUT = LOW (TON); SDC = 1 −

60



%

H.5.5

switch-on time horizontal drive pulse



1175



ms

H.5.6

switch-off time horizontal drive pulse



43



ms

2003 Nov 11

IO = 10 mA

202

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT H.6.1

required input current during flyback pulse

note 5

100



300

µA

H.6.2

output voltage

during burst key

4.5

5.0

5.5

V

during blanking

2.8

3.0

3.2

V

1.7

2.0

2.3

V

burst key pulse

3.3

3.5

3.7

µs

vertical blanking, note 60



14/9.5



lines

4.8

5.0

5.2

µs



tbf



V

Hz

H.6.3

clamped input voltage during flyback

H.6.4

pulse width

H.6.5 H.6.6

delay of start of burst key to start of sync

H.6.7

output voltage of H/V timing signal

CSY = 1

VERTICAL OSCILLATOR; NOTE 61 H.7.1

free running frequency



50/60



H.7.2

locking range

45



64.5/72 Hz

H.7.3

divider value not locked



625/525



lines

H.7.4

locking range

434/488



722

lines/ frame



1.8



V



1



mA

VERTICAL RAMP GENERATOR H.8.1

sawtooth amplitude (peak-to-peak value)

VS = 1FH; C = 150 nF; R = 39 kΩ

H.8.2

discharge current

H.8.3

charge current set by external resistor

note 62



14



µA

H.8.4

vertical slope

63 steps; see Fig. 88

−20



+20

%

H.8.5

charge current increase

f = 60 Hz



19



%

H.8.6

LOW level of ramp



1.5



V



1.0



mA

VERTICAL DRIVE OUTPUTS H.9.1

differential output current (peak-to-peak value)

VA = 1FH

H.9.2

common mode current



400



µA

H.9.3

output voltage range

0



2.5

V

EHT TRACKING/OVERVOLTAGE PROTECTION H.10.1

input voltage

1.2



2.8

V

H.10.2

scan modulation range

−5



+5

%

H.10.3

vertical sensitivity



6.3



%/V



−6.3



%/V

+120



−120

µA



3.9



V

H.10.4

EW sensitivity

H.10.5

EW equivalent output current

H.10.6

overvoltage detection level

2003 Nov 11

when switched-on note 57

203

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DE-INTERLACE H.11.1

first field delay



0.5H



EW WIDTH; NOTE 63 H.12.1

control range

100



65

%

H.12.2

equivalent output current

0



700

µA

H.12.3

EW output voltage range

1.0



5.0

V

H.12.4

EW output current range

0



1200

µA

63 steps; see Fig. 91

EW PARABOLA/WIDTH H.13.1

control range

63 steps; see Fig. 92

0



23

%

H.13.2

equivalent output current

EW=3FH; CP=11H; TC=1FH 0



460

µA

EW UPPER/LOWER CORNER/PARABOLA −55

H.14.1

control range

63 steps; see Fig. 93

H.14.2

equivalent output current

PW=3FH; EW=3FH; TC=1FH −262



+55

%



+262

µA

EW TRAPEZIUM H.15.1

control range

63 steps; see Fig. 94



+5

%

H.15.2

equivalent output current

EW=1FH; CP=11H; PW=1FH −100

−5



+100

µA

VERTICAL AMPLITUDE H.16.1

control range

63 steps; see Fig. 87

80



120

%

H.16.2

equivalent differential vertical drive output current (peak-to-peak value)

SC = 0EH

800



1200

µA

63 steps; see Fig. 89

−5



+5

%

−50



+50

µA

−10



25

%

85



117

%

VERTICAL SHIFT H.17.1

control range

H.17.2

equivalent differential vertical drive output current (peak-to-peak value)

S-CORRECTION H.18.1

control range

63 steps; see Fig. 90

VERTICAL LINEARITY H.18.2

control range, ratio bottom/top of 63 steps; see Fig. 95; screen (full screen linearity VSH=1FH; SC=0; setting) VL1/VL0=0/0

VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); NOTE 64 H.19.1

vertical expand factor

0.75



1.38

H.19.2

output current limiting and RGB blanking



1.05



−18



19

VERTICAL SCROLL H.20.1

2003 Nov 11

Control range (percentage of nominal visible picture amplitude)

vertical zoom setting at 3FH

204

CONFIDENTIAL

%

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Colour demodulation part CHROMINANCE AMPLIFIER D.1.1

ACC control range

D.1.2

change in amplitude of the output signals over the ACC range

D.1.3

threshold colour killer ON

D.1.4

hysteresis colour killer OFF

26





dB





2

dB

CHSE1/CHSE0 = 0/0

−30





dB

strong signal conditions; S/N ≥ 40 dB; note 11



+3



dB

noisy input signals; note 11



+1



dB



3.0



note 65

D.1.5 ACL CIRCUIT; NOTE 66 D.2.1

chrominance burst ratio at which the ACL starts to operate

REFERENCE PART

Phase-locked loop D.3.1

catching range

all standards

±500





Hz

D.3.2

phase shift for a ±400 Hz deviation of the oscillator frequency

note 11





2

deg

D.5.1

hue control range

63 steps; see Fig.55

±35

±40



deg

D.5.2

hue variation for ±10% VP

note 11



0



deg

D.5.3

hue variation with temperature

Tamb = 0 to 70 °C; note 11



0



deg

HUE CONTROL

DEMODULATORS

General D.6.3

spread of signal amplitude ratio between standards

note 11

−1



+1

dB

D.6.5

bandwidth of demodulators

−3 dB; note 67



650



kHz

PAL/NTSC demodulator D.6.6

gain between both demodulators INTF = 0 G(B−Y) and G(R−Y)

1.26

1.41

1.58

D.6.12

change of output signal amplitude with temperature

note 11



0.1



%/K

D.6.13

change of output signal amplitude with supply voltage

note 11





±0.1

dB

D.6.14

phase error in the demodulated signals

note 11





±5

deg

2003 Nov 11

205

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SECAM demodulator D.7.1

black level off-set





7

kHz

D.7.2

pole frequency of deemphasis

77

85

93

kHz

D.7.3

ratio pole and zero frequency



3



D.7.4

non linearity





3

%

D.7.5

calibration voltage

1.8

2.3

2.8

V

SBO1/SBO0 = 1/0

Base-band delay line D.8.1

variation of output signal for adjacent time samples at constant input signals

−0.1



0.1

dB

D.8.2

residual clock signal (peak-to-peak value)





5

mV

D.8.3

delay of delayed signal

63.94

64.0

64.06

µs

D.8.4

delay of non-delayed signal

40

60

80

ns

D.8.5

difference in output amplitude with delay on or off





5

%

COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT)

PAL/SECAM mode; (R−Y) and (B−Y) not affected D.9.1

ratio of demodulated signals (G−Y)/(R−Y)



−0.51 ±10%



D.9.2

ratio of demodulated signals (G−Y)/(B−Y)



−0.19 ±25%



NTSC mode; the matrix results in the following signals (nominal hue setting) MUS-bit = 0 D.9.6

(B−Y) signal: 2.03/0°

2.03UR

D.9.7

(R−Y) signal: 1.59/95°

−0.14UR + 1.58VR

D.9.8

(G−Y) signal: 0.61/240°

−0.31UR − 0.53VR

MUS-bit = 1 D.9.9

(B−Y) signal: 2.03/0°

2.03UR

D.9.10

(R−Y) signal: 1.59/102°

−0.24UR + 1.55VR

D.9.11

(G−Y) signal: 0.61/236°

−0.31UR − 0.51VR

REFERENCE SIGNAL OUTPUT/SWITCH OUTPUT; NOTE 68 D.10.1

reference frequency

CMB1/CMB0 = 01

D.10.2

output signal amplitude (peak-to-peak value)

CMB1/CMB0 = 01

D.10.3

output level (mid position)

CMB1/CMB0 = 01

1.9

2.1

2.3

V

D.10.4

SWO output level LOW

CMB1/CMB0 = 10





0.8

V

D.10.5

SWO output level HIGH

CMB1/CMB0 = 11

4.5





V

2003 Nov 11

206

CONFIDENTIAL

3.58/4.43 0.2

0.25

MHz 0.3

V

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Control part SATURATION CONTROL; NOTE 38 C.1.1

saturation control range

63 steps; see Fig.57

52





dB

63 steps; see Fig.58



20



dB

CONTRAST CONTROL; NOTE 38 C.2.1

contrast control range

C.2.2

tracking between the three channels over a control range of 10 dB





0.5

dB

C.2.6

contrast reduction



10



dB



±0.4



V

1.2



V

0.5



2.5

V



3.0



V

BRIGHTNESS CONTROL C.3.1

brightness control range

63 steps; see Fig.59

RGB AMPLIFIERS C.4.1

output signal amplitude (peak-to-peak value)

C.4.101

output signal control range due to the CCC gain loop

C.4.2

maximum signal amplitude (black-to-white)

C.4.3

maximum peak white level

C.4.4

output signal amplitude for the ‘red’ channel (peak-to-peak value)

at nominal luminance input − signal, nominal settings for contrast, white-point adjustment and cathode drive level(CL3-CL0 = 7H)

note 69

− at nominal settings for − contrast and saturation control and no luminance signal to the input (R−Y, PAL)

4.0



V

1.26



V

C.4.41

output impedance



300





C.4.5

nominal black level voltage



1.65



V

C.4.6

black level voltage

when black level stabilisation − is switched-off (via AKB bit)

1.65



V

C.4.61

black level voltage control range AVG bit active; note 70

1.0

1.65

2.3

V

C.4.71

timing of wide blanking with respect to mid sync (HBL = 1); note 71

start of blanking; WBI = 0

3.5



5.9

µs

end of blanking; WBI = 0

7.8



10.2

µs

start of blanking; WBI = 1

9.7



12.1

µs

C.4.72 C.4.73

14.0



16.4

µs

C.4.8

control range of the black-current stabilisation



±0.65



V

C.4.81

RGB output level when RGBL=1



0.8



V

C.4.74

2003 Nov 11

end of blanking; WBI = 1

207

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER C.4.9

PARAMETER

UOCIII series

CONDITIONS

blanking level

difference with black level, note 69

MIN. −

TYP. −0.3

MAX. −

UNIT V

C.4.91

blanking level when RBL = 1



−1.1



V

C.4.10

level during leakage test



−0.07



V

C.4.11

level ‘low’ measuring pulse



0.15



V

C.4.12

level ‘high’ measuring pulse (current setting 220 µA); note 72



0.6



V

C.4.13

adjustment range of the cathode note 69 drive level



±3



dB

C.4.14

variation of black level with temperature





1.0

mV/K

C.4.141

black level off-set adjustment on 63 steps the Red and Green channel



±100



mV

C.4.21

signal-to-noise ratio of the output RGB input; note 73 signals CVBS input; note 73

60





dB

50





dB

residual voltage at the RGB outputs (peak-to-peak value)

at fosc





15

mV

C.4.24

at 2fosc plus higher harmonics −



15

mV

C.4.25

bandwidth of output signals

RGB input; at −3 dB



7



MHz

C.4.26

CVBS input; at −3 dB; fosc = 3.58 MHz



2.8



MHz

C.4.27

CVBS input; at −3 dB; fosc = 4.43 MHz



3.4



MHz

C.4.28

S-VHS input; at −3 dB

5





MHz

HEX code



20H





±3



dB



10



µA



220



µA

C.4.22 C.4.23

note 11

WHITE-POINT ADJUSTMENT C.5.1

I2C-bus setting for nominal gain

C.5.2

adjustment range of the relative R, G and B drive levels

2-POINT BLACK-CURRENT STABILIZATION, NOTES 74 C.6.1

amplitude of ‘low’ reference current

C.6.2

amplitude of ‘high’ reference current; note 72

C.6.3

acceptable leakage current



±75



µA

C.6.4

input impedance during scan



500



kΩ

SLG0/SLG1 = 0/0

BEAM CURRENT LIMITING C.7.1

contrast reduction starting voltage



2.8



V

C.7.2

voltage difference for full contrast reduction



1.8



V

C.7.3

brightness reduction starting voltage



1.7



V

2003 Nov 11

CBS = 0

208

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications NUMBER

PARAMETER

UOCIII series

CONDITIONS

MIN.

TYP.

MAX.

UNIT



2.4



V

voltage difference for full brightness reduction



0.9



V

C.7.5

internal bias voltage



3.3



V

C.7.8

maximum allowable current



1



mA

C.7.31

brightness reduction starting voltage

C.7.4

CBS = 1

FIXED BEAM CURRENT SWITCH-OFF; NOTE 75 C.8.1

discharge current during switch-off

0.85

1.0

1.15

mA

C.8.2

discharge time of picture tube



38



ms

PEAK WHITE LIMITER AND SOFT CLIPPING; NOTES 76 AND 77 C.9.1

CVBS signal amplitude at which PWL range (15 steps); at peak white limiter is activated max. contrast (black-to-white value)

0.40



0.60

V

C.9.2

soft clipper gain reduction



8



dB

maximum contrast; note 77, see Fig.84

General purpose switch output SWO1 (controlled by SWO1 bit) O.1.1

output voltage HIGH

3.5

5.0

5.5

V

O.1.2

output voltage LOW



0.2

0.4

V

O.1.3

sink current

2





mA

O.1.4

source current

2





mA



3.3



V

Vertical guard input and LED drive output; note 78 I/O.1.1

output voltage HIGH

vertical guard activated vertical guard not activated

I/O.1.2

output voltage HIGH





5.5

V

I/O.1.3

output voltage LOW



0.2

0.4

V

I/O.1.4

sink current

2





mA

I/O.1.5

detection level for vertical guard and input port

tbf

3.6

tbf

V

Notes 1. When the 3.3 V supply is present and the µ-Controller is active a ‘low-power start-up’ mode can be activated. When all subaddress bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be switched-on via the STB-bit (subaddress 3DH). In this condition the horizontal drive signal has the nominal TOFF and the TON grows gradually from zero to the nominal value. As soon as the 5 V supply is present the switch-on procedure (e.g. closing of the second loop) is continued. 2. The various parameters in this specification are guaranteed for a supply voltage range between 4.75 V and 5.5 V. For supply voltages between 4.5 V and 4.75 v some output signals may be distorted or clipped, however, the operation of the circuit is not affected at these supply voltages. 3. The supply voltage of the analogue audio part may have a value between 5V and 8V. For a supply voltage of 5V the maximum amplitude of the output signals is 1Vrms. For a supply voltage of 8V the maximum amplitude of the output signals is 2Vrms. 4. On set AGC. 5. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 2003 Nov 11

209

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

6. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as FPLL input signal level). 7. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a digital control circuit which uses the clock frequency of the µ-Controller as a reference. The required IF frequency for the various standards is set via the IFA-IFC bits in subaddress 2FH. When the system is locked the resulting IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz. 8. Measured at 10 mV (RMS) top sync input signal. 9. So called projected zero point, i.e. with switched demodulator. 10. Measured in accordance with the test line given in Fig.60. For the differential phase test the peak white setting is reduced to 87%. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 11. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 12. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.61. 13. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal) 14. The test set-up and input conditions are given in Fig.62. The figures are measured with an input signal of 10 mV RMS. This test can only be carried out in a test set-up in which the test options of the IC can be activated. This because the IF-AGC control input is not available in this IC. 15. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567. 16. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output. The pin can also be used as CVBS input. The selection between both signals is realised by means of the SVO bits in subaddress 39H. 17. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BG standard, curve A (see “Rec. ITU-R BT.470-4”). The indicated values are the difference between the group delay at 4.43 MHz and the group delay at 10 kHz. 18. The time-constant of the IF-AGC is internal and the speed of the AGC can be set via the bits AGC1 and AGC0 in subaddress 30H. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid for the ‘norm’ setting (AGC1-AGC0 = 0-1) and when the PLL is in lock. 19. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the clock frequency of the TCG µ-Controller as a reference and is therefore very accurate. For this reason no maximum and minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The tuning information is supplied to the tuning system via the AFC bits in output byte 04H. The AFC value is valid only when the LOCK-bit is 1. 20. The QSS IF circuit can also be used for the preprocessing of digital TV signals. The modulated signal has to be supplied to the sound IF input (via a suitable filter) and the mixed down I-signal is available at the DVB outputs. The AGC has two modes of operation: the internal mode in which the IC sets the gain with its own reference and an external mode in which the gain can be controlled with an external circuit. In the second case the QSS-IF AGC pin is used as an input to control the IF gain with an external circuit. 21. The reference signal for the I-mixer (frequency 43.008 or 49.152 MHz) is internally generated. It is also possible to supply an external reference signal to the mixer. This external mode is activated by means of the CMB2-CMB0 and IFD bits. The signal has to be supplied to the pin which is normally used as the reference signal output of the colour decoder (REFO).

2003 Nov 11

210

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

22. The weighted S/N ratio is measured under the following conditions: a) The vision IF modulator must meet the following specifications: Incidental phase modulation for black-to-white jumps less than 0.5 degrees. QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation. Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter). b) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound IF. Input level for sound IF 10 mVRMS with 27 kHz deviation. c) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC ratio. This PC/SC ratio is necessary to achieve the S/N(W) values as indicated. 23. The input should be shunted with a resistor of 470 Ω - 10 kΩ 24. If a 10.7MHz FM radio IF signal is supplied to the external 2nd SIF input, an external 10.7MHz bandpass filter must be used. 25. f = 4.5/5.5 MHz; FM: 70 Hz, ± 50 kHz deviation; AM: 1.0 kHz, 30% modulation. 26. f = 5.5 MHz; modulation frequency: 1 kHz, ∆f = ± 27 kHz. 27. Depending on the application (FM or AM reception) the amplitude of the output signal can be increased with 6 dB by the AGN bit in subaddress 33H (FM reception) or AMLOW bit in subaddress 35H (AM reception). The resulting output signal amplitudes are given in Table 268. 28. The signal-to-noise ratio is measured under the following conditions: a) Input signal to the SSIF pin (activated via the CMB2-CMB0 bits) with an amplitude of 100mVRMS, fMOD = 1 kHz and ∆f = 27 kHz b) Output signal measured at the AUDEEM pin. The noise (RMS value) is measured according to the CCIR 468 definition. 29. In the “Mono” versions the deemphasis pin can also be used as additional audio input. In that case the internal (demodulated FM signal) must be switched off. This can be realised by means of the SM (sound mute) bit. When the vision IF amplifier is switched to positive modulation the signal from the FM demodulator is automatically switched off. The external signal must be switched off when the internal signal is selected. 30. The “Stereo” and “AV Stereo” versions have 4 stereo inputs. The maximum output signal amplitude of the selector (1.0 VRMS or 2.0 VRMS) is dependent on the supply voltage (5 V or 8 V) of the audio selector supply pin (VCC8V). 31. Audio attenuator at −6 dB, input signal 500 mVRMS 32. Audio input signal 200 mVRMS. Measured with a bandwidth of 15 kHz and the audio attenuator at −6 dB. 33. Unweighted RMS value, audio input signal 500 mVRMS, audio attenuator at −6 dB. 34. In versions without stereo decoder and digital sound processing circuits an analogue Automatic Volume Levelling (AVL) function can be activated. The pin to which the external capacitor has to be connected can be chosen by means of the AVLE bit (subaddress 34H). When the East-West output is not used (90° picture tubes) the capacitor can be connected to the EW output pin. In 110° applications a choice has to be made between the AVL function and a sub-carrier output / general purpose switch output. The selection must be made by means of the CMB0 to CMB2 bit in subaddress 4AH. More details about the sub-carrier output are given in the parameters D.10. The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level which can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation of the modulation depth of the transmitter. The AVL can be switched on and off via the AVL bit in subaddress 34H. The AVL is active over an input voltage range (measured at the deemphasis output) of 50 to 1500 mVRMS. The AVL control curve is given in Fig.65. The control range of +6 dB to −14 dB is valid for input signals with 50% of the maximum frequency deviation.

2003 Nov 11

211

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

35. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 36. This parameter is measured at nominal settings of the various controls. 37. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1). 38. The contrast and saturation control is active on the internal signal (YUV) and on the external RGB/YUV/YPRPB input. The Text/OSD input can be controlled on brightness only. Nominal contrast is specified with the DAC in position 20 HEX. Nominal saturation as maximum −10 dB. 39. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation. 40. Depending on the setting of the INTF bit (subaddress 42H) the saturation of the output signal is 75% (YUV signal) or 100% (YPRPB signal). The luminance and colour difference out- and inputs can directly be connected. When additional picture improvement ICs (like the TDA 9178) are applied the inputs of these ICs must be ac coupled because of the black level clamp requirement. The output signal of the picture improvement IC can directly be coupled to the luminance and colour difference inputs as long as the dc level of these signals have a value between 1 and 4 V (for the luminance signal) or between 1 and 4 V (for the UV signals). When the dc level of the input signals exceed these levels the signals must be ac coupled and biased to a voltage level within these limits. 41. Test signal: For PAL B, G, H, D, I and N: CCIR-18 multi-burst (see Fig. 66). For PAL M and NTSC M: 100% amplitude FCC multi-burst (see Fig. 67). 42. This control range is valid for a colour carrier frequency of 4.43 MHz. For a colour carrier frequency of 3.58 MHz the control range has a value of ± 190 µs (see also Table 132). 43. Test signal: For PAL B, G, H, D, I and N: 100/0/75/0 EBU colour bar. For PAL M and NTSC M: 100% white 75% amplitude FCC colour bar. 44. When the decoder is forced to a fixed subcarrier frequency (via the CM-bits) the chroma trap is always switched-on, also when no colour signal is identified. In the automatic mode the chroma trap is switched-off when no colour signal is identified. 45. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 46. The ratio between the positive and negative peaks can be varied by means of the bits RPO1 and RPO0 in subaddress 47H. For ratios which are smaller than 1.7 the positive peak is not affected and the negative peak is reduced. 47. The coring can be activated in the low-light part of the picture. This effectively reduces the noise while having maximum peaking in the bright parts of the picture. The setting the video content at which the coring is active can be adapted by means of the COR1/COR0 bits in subaddress 47H. 48. For video signals with a black level which deviates from the back-porch blanking level the signal is “stretched” to the blanking level. The amount of correction depends on the IRE value of the signal (see Fig.72). The black level is detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in subaddress 45H. The values given in the specification are valid only when the luminance input signal has an amplitude of 1 Vp-p. 49. The Dynamic Skin Tone Correction circuit is designed such that it corrects (instantaneously and locally) the hue of those colours which are located in the area in the UV plane that matches to skin tones. The correction is dependent on the luminance, saturation and distance to the preferred axis. Because the amount of correction is dependent on the parameters of the incoming YUV signal it is not possible to give exact figures for the correction angle. The correction angle of 45 (±22.5) degrees is just given as an indication and is valid for an input signal with a luminance signal amplitude of 75% and a colour saturation of 50%. A graphical representation of the control behaviour is given in Figure 73 on page 229.

2003 Nov 11

212

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

50. The gamma control is realised by inserting a non-linear transfer characteristic in the luminance path. The shape of the curve can be adapted by means of the WS1/WS0 bits in subaddress 45H. The control curves are given in Fig. 74. It is possible to make the gamma control dependent on the Average Picture Level (APL). This function is identical to the previous white stretch function. Then the GAM bit (subaddress 44H) must be set to “0”. The control curve can again be adapted by means of the WS1/WS0 bits (see also Fig. 75). When the gamma control is active the colour saturation is adapted to the variation of the luminance linearity. 51. Via the ‘blue stretch’ (BLS bit) function the colour temperature of the bright scenes (amplitudes which exceed a value of 80% of the nominal amplitude) can be increased. This effect is obtained by increasing the small signal gain of the blue channel and decreasing the small signal gain for the red channel for signals which exceed the 80% level. The effect is illustrated in Figure 76 on page 230. 52. When this function is activated (TFR = 1) the black level of the RGB output signals is dependent on the average picture information. For a ‘black’ picture the black level is unaffected and the maximum black level shift for a complete ‘white’ picture (100 IRE) is 10 IRE in the direction ‘black’. The black level shift is linearly dependent on the picture content. 53. The SVM is specified for a 2T-pulse input signal with an amplitude (100%) of 700 mVP-P. The coring system on the SVM output signal has to levels. The SVM output signal amplitude is dependent on the setting of the coring and on SVMA (see Fig. 77). 54. The delay between the RGB output signals and the SVM output signal can be adjusted (by means of the SVM2-SVM0 bits in subaddress 48H) so that an optimum picture performance can be obtained. Furthermore a video dependent coring function can be activated. Another feature is that the SVM output signal can be made dependent on the horizontal position on the screen (parabola on the SVM output). The screen is equally divided into 6 parts (see Fig. 78). By multiplying a gain factor with the SVM output signal as a function of the horizontal position several discrete curves can be made. The shape of the curve can be programmed by means of the SPR2-SPR0 bits (in subaddress 48H). 55. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the top sync level. When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 0.4 Vp-p. By means of the SSL bit (subaddress 3FH) the slicing level can be changed to 30% (SSL = 1). The vertical slicing level is dependent on the S/N ratio of the incoming video signal. For a S/N ≤ 24 dB the slicing level is 35%, for a S/N ≥ 24 dB the slicing level is 60%. With the bit FSL (Forced Slicing Level) the vertical slicing level can be forced to 60%. 56. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the POC, FOA, FOB and VID bits in subaddress 3DH. The circuit contains a noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching of the time constant can be automatically or can be set by means of the control bits. The circuit contains a video identification circuit which is independent of the first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is about 22 µs. During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to a minimum. The output current of the phase detector in the various conditions are shown in Table 269.

2003 Nov 11

213

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

57. The ICs have 2 protection inputs. The protection on the second phase detector pin is intended to be used as ‘flash’ protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-on again via the slow start procedure. The protection on the EHT input is intended for overvoltage (X-ray) protection. When this protection is activated the horizontal drive is directly switched-off (via the slow stop procedure). The EHT protection input can also be used to switch-off the TV receiver in a correct way when it is switched off via the mains power switch or when the power supply is interrupted by pulling the mains plug. This can be realised by means of a detection circuit which monitors the main supply voltage of the receiver. When this voltage suddenly decreases the EHT protection input must be pulled HIGH and then the horizontal drive is switched off via the slow stop procedure. Whether the EHT capacitor is discharged in the overscan or not during the switch-off period depends on the setting of the OSO bit (subaddress 3EH, D4). See also note 75. 58. The control range indicates the maximum phase difference at the top and the bottom of the screen. Compared with the phase position at the centre of the screen the maximum phase difference at the top and the bottom of the screen is ±0.75 µs for the parallelogram and ±1.0 µs for the bow correction. 59. During switch-on the horizontal drive starts-up in a soft-start mode. The horizontal drive starts with a very short TON time of the horizontal output transistor, the ‘off time’ of the transistor is identical to the ‘off time’ in normal operation. The starting frequency during switch-on is therefore about 2 times higher than the normal value. The ‘on time’ is slowly increased to the nominal value in a time of about 1175 ms (see Fig.81). The rather slow rise of the TON between 75% and 100% of TON is introduced to obtain a sufficiently slow rise of the EHT for picture tubes with Dynamic Astigmatic Focus (DAF) guns. When the nominal frequency is reached the PLL is closed in such a way that only very small phase corrections are necessary. This ensures a safe operation of the output stage. During switch-off the soft-stop function is active. This is realised by doubling the frequency of the horizontal output pulse. The switch-off time is about 43 ms (see Fig.81). When the ‘switch off command’ is received the soft-stop procedure is started after a delay of about 2 ms. During the switch-off time the EHT capacitor of the picture tube is discharged with a fixed beam current which is forced by the black current loop (see also note 75). The discharge time is about 38 ms. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. 60. The vertical blanking pulse in the RGB outputs has a width of 27 or 22 lines (50 or 60 Hz system). The vertical pulse in the sandcastle pulse has a width of 14 or 9.5 lines (50 or 60 Hz system). This to prevent a phase distortion on top of the picture due to a timing modulation of the incoming flyback pulse. 61. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. During TV reception this divider circuit has 3 modes of operation: a) Search mode ‘large window’. This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) is received). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode ‘narrow window’. This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. The IVWF bit in output byte 03 is set to “1” when 7 succeeding vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.

2003 Nov 11

214

CONFIDENTIAL

Philips Semiconductors

Preliminary specification

Versatile signal processor for low- and mid-range TV applications

UOCIII series

c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz). When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress 3EH. When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequence that the circuit can also be synchronised by signals with a higher vertical frequency like VGA. 62. Conditions: frequency is 50 Hz; normal mode; VS = 1F. 63. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µA variation in E-W output current is equivalent to 20% variation in picture width. 64. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38 of the nominal scan. At an amplitude of 1.06 of the nominal scan the output current is limited and the blanking of the RGB outputs is activated. This is illustrated in Fig. 79. When the vertical amplitude is compressed (zoom factor