Seminar report on

DLX processor For the subject of Architecture of Computer Systems

Supervisor: ing. Róbert Lórencz November 23rd, 2006, 1430-1615

Yann KOWALCZUK David KOUDELA Faculty of Electrical Engineering Czech Technical University in Prague

1. Task of 5th week: stalls A) Instructions 1) Download

an

updated

test

program

program_mem.txt

into

H:\hds_projects\aps2005\work directory 2) Write equations for hazard control logic ( stall and clear signals) which ensures that a program with data hazards is executed correctly. It means that when a data hazard is detected, a stall is enforced in the pipeline. (This pipeline is called to be interlocked.) This problem has several sub-problems: Finding of the stage in the pipeline when data hazards are detected (It should be done as soon as possible.) Defining of the condition which is true when data hazard occurs (You need to understand how the instructions flows through the pipeline and meaning the main control signals). Understanding of the mechanism of inserting stalls in the pipeline (See controlling the pipeline flow section

namely pipeline with stalls).

Defining of stall and clear signal equations for every pipeline stage. (See VHDL subset for writing these equations) B) Solution First, the stall has to be detected in the pipeline. Thus, we have to proceed to this detection depending on the type of instructions: register-register, register-immediate, load, store

When an instruction is fetched, we have to check if the used registers (a

and b for example) are not the same as a result register (from a previous instruction, w for example) in the pipeline stage. In order to run without stall, the instruction using the same register must be in the end of MEM or in WB stage, while the new instruction using the same register is fetched. So, if the same register is used in 2 instructions while in ID or EX stage, a stall must be declared in the IF stage. The ID stage must also be stalled as a result of the previous explanation (recycling), and regarding the following scheme:

1

On the other hand, NOP must be inserted in the ID stage until stall is resolved; this means that the EX stage will be cleared when a stall is detected. Reading in the signals document from the diagram, we can see that used registers a and b, in the ID and EX stages, have the value of 00000 for all instructions, except register-register and store. Destination register w, in the EX and MEM stage, has the value 00000 for store instructions, and a different value for any other one. In our integer pipeline simulation, only RAW (Read After Write) hazard can occur, no WAW (Write After Write) or WAR (Write After Read), and neither hazard between load and store instructions, because of the design of this pipeline. As a result, we obtain: IF_stall