Introduction Transistors The CMOS inverter Technology Scaling Gates Sequential circuits Storage elements Phase-Locked Loops Example: – GOL
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Storage elements
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GOL – Rad tolerant Gbit/s serializer •
The GOL is a parallel-to-serial data transmitter: – At a rate of 40 MHz, it accepts 16 or 32-bit parallel data in – It generates a serial bit stream out at: • 0.8 Gbit/s for 16-bit in • 1.6 Gbit/s for 32-bit in
– It is compatible with two standard line encoding protocols: • The G-Link • The 8B/10B
– Two serial output drivers • 50 Ω differential • Laser/VCSEL
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Storage elements
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Data Serializers
Serial Data Parallel Data (N bits) Load
Shift-Register
Bit Clock
•
What is a serializer?
•
– A shift register! – Parallel loaded at the “word rate” – “Emptied” at the “bit rate” – “Bit rate” = (#bits in word) × (word rate)
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Would a simple shift register work?
Storage elements
– NO! – There is no information about the bit boundaries (clock) – There is no information about the word boundaries (frame)
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Data Serializers • •
To be useful, a serializer must convert the raw data into a “line encoded” version. The line code “adds”: –
– – – –
A number of “redundant” bits to the word being transmitted Ensuring DC signal balance Ensuring enough transitions for clock recovery Identifying the frame/word boundaries Providing a somehow limited error checking capability
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•
8B/10B word encoding
•
CMIT word encoding
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– Each 8-bit word is mapped into a 10-bit word – The maximum run length is 5 (enough transitions for clock recovery) – Maximum unbalance between 1s and 0s is ±2
– Adds 4 bits to each 16-bit word – Each frame has a well define master transition – The word to be transmitted is simply flipped or not depending on previous disparity and its own disparity
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40 MHz or 80 MHz 40 MHz
GOL: Architecture
D(31:0)
CIMT Encoder
16/32b
dav
Data Interface
16b
20b
80 MHz or 160 MHz
Word Multiplexer
8B/10B Encoder
cav
LHC clock
40 MHz or 80 MHz
800 Mbit/s or 1.6 Gbit/s
10b
PLL & Clock Generator
Laser Driver
I2C JTAG Config Paulo Moreira
Control & Status Registers
Serializer 50Ω Line Driver Storage elements
out+ out5
GOL: Serializer • Parallel-load shift register: – cascade of flip-flops and 2-to-1 multiplexers
• Operation speed is limited by:
load d D
– Clock to Q delay – Mux delay – Flip-flop setup time
• Maximum frequency:
D
Q
tcq
tmux
Q
tsetup
– 1/(tcq + tmux + tsetup)
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GOL: Serializer • Maximum operation speed – 1.6 GHz ⇒ T = 625 ps
• Technology CMOS 0.25 µm – Static FF t(min) = 1292ps ! (worst case) – Dynamic FF t(min) = 768ps (worst case) – For a safe design (good yield) any of the two FF is too slow
typical worst
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DFF tpd (ps) 145 369
DFF tsup (ps) 60 152
SFF tpd (ps) 309 749
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SFF tsup (ps) 107 296
MUX tpd (ps) 104 247
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GOL: Serializer Word clock: 120MHz 120 MHz word-clock: Bit clock: 800 MHz bit-clock: 600MHz
From the Word Mux word-clock
Register D(1,3,5,7,9)
D(0,2,4,6,8)
load
Load
Q
Shift-Register
I0
(SR-1)
Mux
serial-data
I1
Load
Q
Shift-Register
D
Q
Latch
(SR-2)
bit-clock
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Storage elements
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GOL: Serializer Register
D(0,1,2,3,4,5,6,7,8,9)
word-clock bit-clock load serial-odd (SR-2)
1
3
5
7
9
serial-even (SR-1)
0
2
4
6
8
serial-odd (Latch)
1
5
3
7
9
mux-select (=bit-clock) serial-data
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0
1
2
3
Storage elements
4
5
6
7
8
9
9
GOL Layout
Logic: • Data interface • JTAG • I2C • Control & Status • 8B/10B Encoder • CIMT Encoder • Word Multiplexer
... CMS tracker analogue data link. â The CMS tracker data path. â The linear laser-driver ... Monitoring. Serial/Parallel. Local. Address. Control & Data. Interface.
The CMOS inverter. ⢠Technology. ⢠Scaling. ⢠Gates ..... For acceptable phase margin. Place the zero 1/Ï .... Add VCO phase noise. Update the VCO period ...
D. A. Johns and K. Martin, âAnalog Integrated Circuit Design,â John Wiley & Sons 1997, ISBN 0- ... B. Razavi, âA Study of Phase Noise in CMOS Oscillators,â IEEE Journal on Solid-State ... http://www.ife.ee.ethz.ch/~ichsc/ichsc_chapter11.pdf.
Design of Analog Integrated Circuits and Systems by Kenneth R. ... Design of Analog CMOS Integrated Circuits ... CMOS Circuit Design, Layout, and Simulation.
Clock skew control and frequency multiplication. Ext. CLK. Clock pad. PLL ...... Algorithm: ⢠Slice the time in very thin intervals (much smaller than T vco. ).
The silicon area of large memory cells is dominated by the size of the memory core, it is thus crucial to keep the size of the basic storage cell as small as possible.
An active low pass filter. ⢠A charge-pump and a capacitor .... Can we run the starved inverter infinitely slow?. ⢠... Signal and the Inverted signal available.
that of a DLL you notice some similarities but as well some very fundamental differences: .... 3rd always buffer the VCO signal to make the transfer ..... âMonolithic Phase-Locked Loops and Clock Recovery Circuits Theory and Design,â ..... In one
... pattern to the wafer surface. â Process the wafer to physically pattern each layer of the IC ... (photo resist: light-sensitive organic polymer). ⢠The photoresist is exposed to ultra violet light: ... active by an rf-generated plasma anisotr
NRZI non-return to zero invert on ones. â Manchester and Bi-Phase Mark. â 3B/4B, 5B/6B and 8B/10B, done in groups of bits before serialization. BiPhase Mark.
CMOS power budget: â Dynamic power consumption: ⢠Charging and discharging of capacitors. â Short circuit currents: ⢠Short circuit path between power rails ...
Tx. Detector channel. LHC clock (40MHz). Gain. 82 728 chan n e ls (barrel +. 2 en d caps). Radiation hard environment. CMS Electromagnetic Calorimeter.
Dec 17, 2004 - M.J.M. Pelgrom et al., âA 25-Ms/s 8-bit CMOS A/D Converter for Embedded Applicationâ, ... components can be attributed to two classes of effects. .... Technical Digest of the IEEE International Electron Device Meeting 1997, pp ...
May 20, 2007 - Below an excerpt form correspondence with Hans Camenzind: ..... This means that any spectral content of the phase noise that is above 10 ...
in the vernier scale (lower) lines up with a tick mark in the reference scale (upper). [36]. 38 ..... Almasi, L. et al., New TDC electronics for a PesTOF tower â in NA49, ... Mota, M., A high-resolution Time-to-Digital Converter â users manual, C
Dec 17, 2004 - The definition of âMoore's Lawâ has come to refer to almost anything related to ..... The following data are taken from the design manuals of different CMOS technologies. N. D. Arora et al., "Modeling the Polysilicon Depletion Effe
possible then, the speed limitation should come from the switching transistor themselves, in ..... found in practical circuits makes it a circuit to be avoided. .... depends on the phase detector gain, which depends on the power supply voltage Vdd.
