K40IN BLOCK DIAGRAM

DQ0. 5. DQ1. 7. DQ2. 17. DQ3. 19. DQ4. 4. DQ5. 6. DQ6. 14. DQ7. 16. DQ8. 23. DQ9. 25. DQ10. 35. DQ11. 37. DQ12. 20. DQ13. 22. DQ14. 36. DQ15. 38. DQ16.
1MB taille 1 téléchargements 122 vues
5

4

K40IN BLOCK DIAGRAM

3

2

1

CPU MERON;PENRYN

XDP

D

Discharge Circuit Page 67

Page 3~5

D

FSB 800MHz;1066MHz

Thermal Sensor

LCD Panel Page 45

PWM Fan

DC Conn. Page 60

Page 50

Onboard DRAM

Page 46

Page 41

Page 50

Page 6,8~9

CRT

Switch & LED

Maxim MAX6657

DDRII So-DIMMx2 800

DDR2

Page 57

Skew Holes

Battery Conn.

Page 65

Page 60

Page 9~10

ODD Page 51

MCP75 HDD

C

Power

Page 54

PCIE x1

C

VCORE

MiniCard

Page 80

WWAN

System

Page 53

Page 81

GigaLAN

1.05VSUS

REALTEK 8112

Transformer

Page 82

Page 33~34

DDR & VTT

LPC

Page 83

Debug Conn.

+1.5VS

Page 44 B

B

Page 84

Touchpad

EC

Page 31

Charger

8502

Keyboard Page 31

Page 88

USB

Page 30

MiniCard

SPI ROM

Detect

WWAN

Page 30

Page 90

Page 53

USB Port

Load Switch

Page 52

Audio Amp

Azalia Codec

Page 39

A

USB Port

Azalia

Page 91

Page 45

Power Protect

Page 52

Page 92

USB Port

Realtek ALC269

Jack

CMOS Camera

Page 52

Page 36

A

Page 37

USB Port Page 52



Title :Block Diagram

CardReader

Page 17~26

ASUSTeK COMPUTER INC. NB6

Page 54

Size

5

4

3

2

Tony Kao

Project Name

Custom Date:

Engineer:

Rev

G71G

1.0

Friday, February 13, 2009

Sheet 1

1

of

91

A

B

C

D

E

Reset

1

1

IC

AC_BAT_SYS

+5VA +3VA +3VA_EC

1 3

6

PWR_SW#

2 +3VA_EC

5 PM_RSMRST#

EC

7 PM_PWRBTN#

IT8752 VSUS_ON

Power On SWITCH

8

SLP_S5#

PWRGD_SB

10

PWRBTN#

To EC SLP_S3#

SUSC#_PWR

+0.9V +1.8V +3V +5V +12V 1Kohm

9 SUSC_EC#

12

15 PM_PWROK

MCP79 PS_PWRGD PCI_RESET#

11

21

STR_EN#

H_PWRGD

9

SUSB_EC#

SUS_PWRGD

ALL_SYSTEM_PWRGD

2

4

SUSC_EC#

CPU_PWRGD +1.05VSUS +3VSUS +5VSUS +12VSUS

2

20

14 VRM_PWRGD 13 CPU_VRON

22

CPU_VLD CPU_RESET#

H_CPURST#

Penryn

CPUVDD_EN LPC_RESET#

19

17

CPU_VRON

SUSB#_PWR

MCP_VDD_CORE +1.05VS +1.5VS +1.8VS +2.5VS +3VS +5VS +12VS

CPU_PWRGD

3

18

ROMSTRAP To ROM Unused!!

16

Power On Sequence

11 1Kohm

3

SUSB_EC#

1

22

+VCORE

4

4

5

5



Title : Schematic Information ASUSTeK COMPUTER INC. NB6 Size A2 B

C

D

Keirui Shen Rev

G71G

Date: Friday, February 13, 2009 A

Engineer:

Project Name

E

1.0 Sheet

2

of

91

5

4

H_A#[35:3]

1

H_D#[63:0] H_A#[35:3]

QC

+VCCP_CPU

+VCCP_CPU 2

H_D#[63:0]

[17]

2

2

[17]

3

H_REQ#[4:0]

[17] H_REQ#[4:0]

1

100Ohm 1% 1 2

LOCK#

H4 C1 F3 F4 G3 G2

HIT# A[17]# HITM# A[18]# A[19]# BPM[0]# A[20]# BPM[1]# A[21]# BPM[2]# A[22]# BPM[3]# A[23]# PRDY# A[24]# PREQ# A[25]# TCK A[26]# TDI A[27]# TDO A[28]# TMS A[29]# TRST# A[30]# DBR# A[31]# A[32]# THERMAL A[33]# A[34]# A[35]# PROCHOT# ADSTB[1]# THRMDA THRMDC A20M# FERR# THERMTRIP# IGNNE#

G6 E4

H_HIT# H_HITM#

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

XDP_BPM#0 [67] XDP_BPM#1 [67] XDP_BPM#2 [67] XDP_BPM#3 [67] XDP_BPM#4 [67] XDP_BPM#5 [67] XDP_TCK [67] XDP_TDI [67] XDP_TDO [67] XDP_TMS [67] XDP_TRST# [67] XDP_DBR# [67]

M4 N5 T2 V3 B2 C3 D2 D22 D3 F6

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10

+VCCP_CPU

R0315 1KOhm 1%

[17] [17] [17]

H_DSTBN#1 H_DSTBP#1 H_DINV#1

R0317 2 R0318 2

R0316 2KOhm 1%

A22 A21

CLK_CPU_BCLK#

GTL_REF 1% 1 1KOhm 1% 1 1KOhm T0304 1

T0306 R0320 T0307 0.1UF/10V

1

C0301 0.1UF/10V

[17]

H CLK BCLK[0] BCLK[1]

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

2

STPCLK# LINT0 LINT1 SMI#

H_DSTBN#0 H_DSTBP#0 H_DINV#0

1.1G Stuff

H_THRMTRIP# [5,17] CLK_CPU_BCLK

D5 C6 B4 A3

[17] [17] [17]

[17] [17]

D21 H_PROCHOT_S# A24 CPU_THRM_DA [50] B25 CPU_THRM_DC [50] C7

H_CPURST#_XDP [67]

R0337

1

XDP/ITP SIGNALS

[17] [17] [17] [17] [17]

2

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

H_LOCK# [17] H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY#

T317

[17]

2

H_INIT#

1 1

[17] CPU_BSEL0 [17] CPU_BSEL1 [17] CPU_BSEL2

AD26 C23 D25 C24 AF26 AF1 A26

GTLREF MISC TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

B22 B23 C21

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

BSEL[0] BSEL[1] BSEL[2]

COMP[0] COMP[1] COMP[2] COMP[3]

R26 U26 AA1 Y1

DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

E5 B5 D24 D6 D7 AE6

2

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

BPM_2[2]#

H_DSTBN#2 [17] H_DSTBP#2 [17] H_DINV#2 [17]

C

QC

Comp 0,2: Zo=25 Ohm, trace length < 0.5" Comp 1,3: Z0=50 Ohm, trace length < 0.5"

DC

Comp 0,2: Zo=27.4 Ohm, trace length < 0.5" Comp 1,3: Z0=55 Ohm, trace length < 0.5"

H_DSTBN#3 [17] H_DSTBP#3 [17] H_DINV#3 [17] H_COMP0 H_COMP1 H_COMP2 H_COMP3

H_DPW R#

BSEL1

1

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#

R344 51Ohm

R0311 R0312 R0313 R0314

27.4OHM 54.9Ohm 27.4OHM 54.9Ohm

H_DPRSTP# H_DPSLP#

[17,79] [17]

H_CPUSLP# PM_PSI#

[17] [79]

BCLK

FSB

BSEL2

166

667

L

H

H

200

800

L

H

L

266

1067

L

L

L

1% 1% 1% 1%

2 54.9Ohm 1% R342 H_PW RGD

1

2 R0336

DC

Default Strapping When Not Used

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

SOCKET478B

Zo=55 Ohm, 0.5" max for GTL_REF

[17]

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#

DATA GRP 2

QC

2

CONTROL

D20 H_IERR# B3

[17]

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

1

[17] H_PW RGD_XDP [67]

1KOhm

B

BSEL0 H_DPW R#

[17]

+VCCP_CPU

XDP_BPM#5 XDP_TDI XDP_TDO XDP_TMS

R0302 R303 R304 R305

1 1 1 1

2 2 2 2

XDP_DBR#

R0306

1

2 1KOhm

XDP_TCK R307 XDP_TRST# R0308

1 1

2 51Ohm 2 649Ohm 1%

51Ohm 51Ohm 51Ohm 51Ohm

+VCCP_CPU 1%

+3VS [17] H_PROCHOT_S#

R0310 68Ohm

H_PROCHOT_S#

[30]

PW RLIMIT#

QC

3

S 2

G

Q0301 H2N7002 11 THRO_CPU

[30]

2

Default Strapping When Not Used

1 RB751V-40

D

Place R0304 & R0306 for XDP function

A

2 D0301

3

1

SOCKET478B

2

T320

BPM_2[1]# BPM_2[0]# 1CPU_THRM_DA_QC 1CPU_THRM_DC_QC BPM_2[2]# T0313 1 T0314 1 GTL_REF2 T316 1 T318 1 H_TDO_M T319 1 H_TDI_M

H_BR0#

1

H_STPCLK# H_INTR H_NMI H_SMI#

F1

1

1

H_DEFER# [17] H_DRDY# [17] H_DBSY# [17]

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

DATA GRP 3

1 [17] [17] [17] [17]

T0321

A6 A5 C4

H5 F21 E1

[17] [17] [17]

RESET# RS[0]# RS[1]# RS[2]# TRDY#

ICH

[17] H_A20M# [17] H_FERR# [17] H_IGNNE#

1

IERR# INIT#

H_ADS# H_BNR# H_BPRI#

RESERVED

T0320

BR0#

H1 E2 G5

DATA GRP 1

H_ADSTB#1

DEFER# DRDY# DBSY#

ADDR GROUP 1

[17]

Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1

ADS# BNR# BPRI#

D

+VCCP_CPU U8802B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

DATA GRP 0

K3 H2 K2 J3 L1

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

C

B

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_ADSTB#0

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

ADDR GROUP 0

[17]

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1

BPM_2[1]#

T0319 1

U8802A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

BPM_2[0]#

1

T0318

D

R343 51Ohm

1

R0342 51Ohm

Place beside CPU ball out

A



Pin B2 M4 N5 left as NC for QC design (BPM_2# [2] BPM_2#[1] BPM_2[0])

Pin T2 V3 change to QC Thermal Diode detect (THRMDA_2 THRMDC_2)

Title : Penryn CPU (1)

mount QC : /QC unmount QC : /[email protected]

Engineer: Size

Project Name

Rev

Custom Date: 5

4

3

2

1.0 Sheet

Friday, February 13, 2009 1

3

of

91

5

4

3

2

1

U8802D

+VCORE

+VCORE U8802C

BR1#

R0410 1

B

20Ohm /[email protected]

VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

VCCA1 VCCA2

B26 C26

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AD6 AF5 AE5 AF4 AE3 AF3 AE2

VCCSENSE

AF7

VSSSENSE

AE7

T0401

+VCCP_CPU

T402 +VCCA_CPU 120 mA

+1.5VS

+VCCA_CPU 1

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

C0402 0.01UF/50V

7 7 5 3 1 1 5 3

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

R0401

10K 10K 10K 10K 10K 10K 10K 10K 1

2

VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

1

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67

2

C

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

8 8 6 4 2 2 6 4 2

RN0401D RN0402D RN0401C RN0401B RN0401A RN0402A RN0402C RN0402B

C0401 10UF/6.3V

VR_VID0 VR_VID1 VR_VID2 VR_VID3 VR_VID4 VR_VID5 VR_VID6

100Ohm 1%

[7,79] [7,79] [7,79] [7,79] [7,79] [7,79] [79]

+VCORE VCCSENSE [79] VSSSENSE [79]

1

D

SOCKET478B

R0402 100Ohm 1%

+VCCP_CPU

2.0G-G71G

1

2

+VCORE

R0405 0Ohm

A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 1 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 1GTLREF_CTRL_RF8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81

VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 1 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 1 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 BPM_2[3]# 1 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

D

T403

C

T404

B

T405

+VCCP_CPU 2

5 10

5 10

5 10 1KOhm RP1D

1KOhm RP1G 4

1KOhm RP1F 8

5 10

1KOhm RP1E 7

1KOhm RP1B 6

5 10

5 10

5 10 1KOhm RP1A 2

1KOhm RP1H 1

2

3

G70G R1.0 0226 for Quad-Core CPU

2 BR1# @ 0Ohm R0409

1KOhm RP1C 9

1

H_BR1#

5 10

SOCKET478B [17]

R0411 51Ohm A

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

BPM_2[3]#

1

A

G71G 1.2G



Title : Penryn CPU (2) Engineer: Size

Project Name

Rev

Custom Date: 5

4

3

2

1.1 Sheet

Friday, February 13, 2009 1

4

of

91

2

@

@

@

@

@

@

@

1 2

C0526 10UF/6.3V

C0509 10UF/6.3V

D

1

1 C0537 0.1UF/10V

2

1 C0534 0.1UF/10V

2

1 C0535 0.1UF/10V

2

1

1 C0538 0.1UF/10V

2

150UF/4V

C0514 0.1UF/10V

C0536 0.1UF/10V

C0533 10UF/6.3V

Decoupling guide from Intel

C0529 10UF/6.3V

@

+VCORE Mid-Frequency Capacitor Intel: 22UF *32 F3S: 10UF *16 A7S: 10UF *10 ....11/17 V1V: ? +VCCP Decoupling Capacitor Intel: 270UF *1, 0.1UF *6 F3S: 100UF *1, 0.1UF *4 V1V: ?

C0532 10UF/6.3V

C

@

CE0501

VCORE 22uF/10V r 10uF * 32pcs 330uF/2V * 6pcs VCCP 0.1uF * 6pcs 150uF * 1pcs ? 10uF * 1pcs ?

1 2

C0505 10UF/6.3V

+

@

1

2

1 C0510 10UF/6.3V

1 C0513 10UF/6.3V

2

2

C0506 10UF/6.3V

2

1 C0503 10UF/6.3V

1

2

1 C0520 10UF/6.3V

1 C0501 10UF/6.3V

2

2

C0507 10UF/6.3V

2

1 C0511 10UF/6.3V

1

2

1 C0522 10UF/6.3V

1 C0504 10UF/6.3V

2

2

C0516 10UF/6.3V

2

1 C0528 10UF/6.3V

1

2

1 C0524 10UF/6.3V

1 2

C0539 10UF/6.3V

@

1

2

1 2

2

C0512 10UF/6.3V

@

2

C0517 10UF/6.3V

1

2

C0525 10UF/6.3V

1

2

1

2

1

C0527 10UF/6.3V

+VCCP_CPU

JP0501 2MM_OPEN_5MIL @ 1 1 2 2

2

1 C0519 10UF/6.3V

2

1 C0521 10UF/6.3V

2

1 C0530 10UF/6.3V

2

1 C0502 10UF/6.3V

2

1 C0523 10UF/6.3V

2

1 C0515 10UF/6.3V

2

1 C0518 10UF/6.3V

2

1 C0531 10UF/6.3V

2

C0508 10UF/6.3V

2

2

1

1

+VCCP

D

1

+VCCP Decoupling Capacitor (Place near CPU)

38A for Penryn

1

+VCORE

3

2

4

2

5

@

C

B

B

1

+VCCP_CPU

SR2 49.9Ohm [3,17] H_THRMTRIP#

A

2

A



Title : CPU CAPS Engineer: Size

Project Name

Rev

Custom Date: 5

4

3

2

1.0 Sheet

Friday, February 13, 2009 1

5

of

91

5

[8,9,18]

4

3

M_A_A[0:14]

M_A_DQ[0:63]

2

1

[8,18]

DIMM_A1A

C

[8,23,53] [8,23,53] [9,18] [9,18] [8,18] M_A_DM[0..7]

[8,18] M_A_DQS[0:7]

[8,18] M_A_DQS#[0:7]

B

SMB_CLK_S SMB_DAT_S

107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119

M_ODTA0 M_ODTA1 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

10 26 52 67 130 147 170 185

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186

BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

DIMM_A1B

112 111 117 96 95 118 81 82 87 103 88 104

+3VS U8803 EMI_SPRING_PAD

GND

GND

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

199 1

U8804 EMI_SPRING_PAD

2

M_A_BS0 M_A_BS1 M_CSA#0 M_CSA#1 MA_CLK_DDR0 MA_CLK_DDR#0 MA_CLK_DDR1 MA_CLK_DDR#1 M_CKEA0 M_CKEA1 M_A_CAS# M_A_RAS# M_A_W E#

M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ3 M_A_DQ1 M_A_DQ0 M_A_DQ7 M_A_DQ2 M_A_DQ8 M_A_DQ12 M_A_DQ11 M_A_DQ14 M_A_DQ9 M_A_DQ13 M_A_DQ15 M_A_DQ10 M_A_DQ17 M_A_DQ16 M_A_DQ19 M_A_DQ18 M_A_DQ20 M_A_DQ21 M_A_DQ23 M_A_DQ22 M_A_DQ29 M_A_DQ28 M_A_DQ26 M_A_DQ27 M_A_DQ25 M_A_DQ24 M_A_DQ30 M_A_DQ31 M_A_DQ36 M_A_DQ32 M_A_DQ35 M_A_DQ34 M_A_DQ33 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ45 M_A_DQ44 M_A_DQ46 M_A_DQ47 M_A_DQ40 M_A_DQ41 M_A_DQ43 M_A_DQ42 M_A_DQ48 M_A_DQ49 M_A_DQ54 M_A_DQ55 M_A_DQ53 M_A_DQ52 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ57 M_A_DQ62 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ58

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

1

[8,9,18] [8,9,18] [9,18] [9,18] [18] [18] [18] [18] [9,18] [9,18] [8,9,18] [8,9,18] [8,9,18]

+1.8V

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

1

[8,9,18] M_A_BS2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

1

D

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85

1

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

DC1 0.1UF/16V /X

GND

VDDSPD

83 120 50 69 163 DIMM_VREF

NC1 NC2 NC3 NC4 NCTEST

1

VREF

201 202

GND0 GND1

203 204

NP_NC1 NP_NC2

47 133 183 77 12 48 184 78 71 72 121 122 196 193 8

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

D

C

DDR_DIMM_200P GND

GND

B

DDR_DIMM_200P

2

DC4

1

DC3

1

1

1

SMB_CLK_S SMB_DAT_S

DC5

2

DR1 1KOhm 1% /X

DC7 100PF/50V /X

1

+1.8V

+1.8V

DC2

Close to DIMM

1

+0.9V

Close to DIMM

DC8 100PF/50V /X

2

DIMM_VREF

1

Power Cap Close to DIMM

DIMM_VREF

2

A

1

GND

DIMM_VREF

[8]

GND

1

1

120Ohm/100Mhz

DR2 1KOhm 1% /X

2

1UF/10V /X

2

1UF/10V /X

2

1UF/10V /X

2

2

2

DL1 1UF/10V /X

DC6 0.1UF/10V

A

GND

Title :

GND ASUSTeK COMPUTER INC. NB6 Size

Engineer:

Project Name

Rev

A3 Date: 5

4

3

2

1.0 Sheet

Friday, February 13, 2009 1

6

of

91

5

4

3

2

1

+VCCP_CPU

4

1

4

1

3

6

3

6

3

1

/@/cpu_ov

Q0710B UM6K1N

5

/@/cpu_ov

/@/cpu_ov D

/@/cpu_ov GND

G

RN0703A 1KOhm

RN0703D 1KOhm

RN0703C 1KOhm

VR_VID0 /@/cpu_ov

VR_VID1 /@/cpu_ov

VR_VID2 /@/cpu_ov

H2N7002 Q0510

2 S

4

2

4

D

6

3 11

RN0703B 1KOhm

RN0704A 1KOhm

RN0704B 1KOhm

VIDPUPSW #

VR_VID3 /@/cpu_ov

VR_VID4 /@/cpu_ov

VR_VID5 /@/cpu_ov

3

1

3

GND

1

GND

/@/cpu_ov

Q0710A UM6K1N

2

2

/@/cpu_ov GND

/@/cpu_ov

Q0709B UM6K1N

5

5

2

VIDSEL1

Q0709A UM6K1N

2

/@/cpu_ov

Q0702A UM6K1N /@/cpu_ov 1

[23]

R3050 1 10KOhm 2 1% @

Q0708B UM6K1N

5

8

6

6 2

VIDSEL0

Q0708A UM6K1N

2

Q0702B UM6K1N

5

1

[21]

Q0701A UM6K1N /@/cpu_ov

+5VS

/@/cpu_ov

4

5 D

R3049 1 10KOhm 2 1%

RN0701B

2

Q0701B UM6K1N

/@/cpu_ov

10KOhm 4

3

3

3

RN0701C

4

10KOhm 6

3

5

6

+3VS

4

VR_VID1

+3VS

7

VR_VID0

+3VS

[21] /@/cpu_ov

3 Q0714A UM6K1N

5 /@/cpu_ov

[21] VIDPUPSW 1

1

2 /@/cpu_ov

[21] VIDPUPSW 1

Q0714B UM6K1N

+5VS

4

6

GND

RN0702D GND

8

[21] VIDPUPSW 1

GND

7 VR_VID0 VR_VID1 VR_VID2 VR_VID3 VR_VID4 VR_VID5 VR_VID6

10KOhm /@/cpu_ov

C

+5VS RN0704D 8 VR_VID2

C

RN0702C

6

5

5

1KOhm /@/cpu_ov

6 10KOhm /@/cpu_ov

+3VS

2 /@/cpu_ov

Q0706A UM6K1N /@/cpu_ov

GND GND

GND

2 /@/cpu_ov

B

GND 3

Q0715B UM6K1N

[21] VIDPUPSW 1 GND

Q0706B UM6K1N

Q0716A UM6K1N

[21] VIDPUPSW 1

GND

5 /@/cpu_ov

Q0716B UM6K1N 4

[21] VIDPUPSW 1

VIDSEL5

/@/cpu_ov GND

3 5 /@/cpu_ov

Q0705A UM6K1N /@/cpu_ov [23]

2

6

[21] VIDPUPSW 1

Q0715A UM6K1N 1

2 /@/cpu_ov

VIDSEL4

RN0702B

5

1

B

[23]

4

6

GND

10KOhm 4 /@/cpu_ov

4

6 /@/cpu_ov GND GND

3 Q0705B UM6K1N

5

3

RN0701A

4

10KOhm 2 /@/cpu_ov

6

1

1

/@/cpu_ov GND

VR_VID5 +3VS

1

1

+3VS

Q0704A UM6K1N /@/cpu_ov

2

VIDSEL3

VR_VID4 Q0704B UM6K1N

5

1

RN0701D

3

6

Q0703A UM6K1N /@/cpu_ov [23]

2

10KOhm 8 /@/cpu_ov

4

5

VIDSEL2

7 Q0703B UM6K1N

/@/cpu_ov

3

RN0702A

6

10KOhm 2

3

1

[23]

VIDPUPSW #

7 1KOhm /@/cpu_ov

VR_VID3

4

+3VS

RN0704C

[4,79] [4,79] [4,79] [4,79] [4,79] [4,79] [4,79]

GND

A

A



Title :DDR3 SO-DIMM_0 ASUSTeK COMPUTER INC. NB6 Size

5

4

3

2

Vincent Chung

Project Name

Custom Date:

Engineer:

Rev

G71V

1.0 Sheet

Friday, February 13, 2009 1

7

of

91

5

4

3

[6,9,18] M_A_A[0:14]

M_A_DQ[0:63]

2

1

[6,18]

+1.8V

DIMM_B1A

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195

BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA

114 119

ODT0 ODT1

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

10 26 52 67 130 147 170 185

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

[6,9,18] M_A_BS2

C

+3VS

[6,9,18] [6,9,18] [9,19] [9,19] [19] [19] [19] [19] [9,19] [9,19] [6,9,18] [6,9,18] [6,9,18]

M_A_BS0 M_A_BS1 M_CSA#2 M_CSA#3 MA_CLK_DDR2 MA_CLK_DDR#2 MA_CLK_DDR3 MA_CLK_DDR#3 M_CKEA2 M_CKEA3 M_A_CAS# M_A_RAS# M_A_WE#

[6,23,53] SMB_CLK_S [6,23,53] SMB_DAT_S [9,19] M_ODTA2 [9,19] M_ODTA3 [6,18] M_A_DM[0..7]

[6,18] M_A_DQS[0:7]

B

[6,18] M_A_DQS#[0:7]

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

DIMM_B1B

+3VS

1

D

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85

M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ3 M_A_DQ1 M_A_DQ0 M_A_DQ7 M_A_DQ2 M_A_DQ8 M_A_DQ12 M_A_DQ11 M_A_DQ14 M_A_DQ9 M_A_DQ13 M_A_DQ15 M_A_DQ10 M_A_DQ17 M_A_DQ16 M_A_DQ19 M_A_DQ18 M_A_DQ20 M_A_DQ21 M_A_DQ23 M_A_DQ22 M_A_DQ29 M_A_DQ28 M_A_DQ26 M_A_DQ27 M_A_DQ25 M_A_DQ24 M_A_DQ30 M_A_DQ31 M_A_DQ36 M_A_DQ32 M_A_DQ35 M_A_DQ34 M_A_DQ33 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ45 M_A_DQ44 M_A_DQ46 M_A_DQ47 M_A_DQ40 M_A_DQ41 M_A_DQ43 M_A_DQ42 M_A_DQ48 M_A_DQ49 M_A_DQ54 M_A_DQ55 M_A_DQ53 M_A_DQ52 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ57 M_A_DQ62 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ58

2

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

DC9 0.1UF/16V /X

GND DIMM_VREF

[6] DIMM_VREF

112 111 117 96 95 118 81 82 87 103 88 104

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

199

VDDSPD

83 120 50 69 163

NC1 NC2 NC3 NC4 NCTEST

1

VREF

201 202

GND0 GND1

203 204

NP_NC1 NP_NC2

47 133 183 77 12 48 184 78 71 72 121 122 196 193 8

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

D

C

DDR2_DIMM_200P GND

GND

B

1.1G modify P/N

DDR2_DIMM_200P

1.1G modify P/N A

A



Title :DDR3 SO-DIMM_1 ASUSTeK COMPUTER INC. NB6 Size B Date: 5

4

3

2

Engineer:

Vincent Chung

Project Name

Rev

G71V Friday, February 13, 2009

1.0 Sheet 1

8

of

91

5

4

3

2

1

+0.9V M_A_A[0:14] [6,8,18] M_B_A[0:14] [10,18] [6,18] [6,18] [6,8,18] [6,18]

47Ohm 47Ohm 47Ohm 47Ohm M_A_A13 47Ohm 47Ohm 47Ohm 47Ohm

M_CKEA0 M_CKEA1 M_A_CAS# M_CSA#0

[6,8,18] M_A_BS0 [6,8,18] M_A_W E# [6,18] M_ODTA1

D

[8,19] [8,19] [8,19] [8,19] [8,19] [8,19]

47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm

M_CSA#2 M_CSA#3 M_ODTA2 M_ODTA3 M_CKEA2 M_CKEA3

[6,8,18] M_A_BS1 [6,8,18] M_A_RAS#

[6,8,18] M_A_BS2 C

3 8 2 4 2 6 7 8

2 1 3 7 5 7 4 1

14 9 15 13 15 11 10 9 15 16 14 10 12 10 13 16

RN0901C RN0901H DRN10B DRN16D DRN11B DRN10F DRN10G DRN16H

D

DRN12B DRN10A DRN10C DRN16G RN0901E RN0901G DRN11D DRN16A

M_A_A4 47Ohm M_A_A1 47Ohm 47Ohm M_A_A10 47Ohm 47Ohm M_A_A2 47Ohm M_A_A0 47Ohm M_A_A3 47Ohm

4 3 6 5 5 8 7 8

13 14 11 12 12 9 10 9

DRN12D DRN12C DRN11F DRN10E DRN11E DRN11H DRN11G DRN10H

M_A_A6 47Ohm M_A_A7 47Ohm 47Ohm M_A_A9 47Ohm M_A_A8 47Ohm M_A_A5 47Ohm M_A_A12 47Ohm M_A_A11 47Ohm

5 6 6 2 8 1 1 7

12 11 11 15 9 16 16 10

DRN12E DRN12F RN0901F RN0901B DRN12H DRN12A RN0901A DRN12G

DC14 1

2

0.1UF/10V

DC16 1

2

0.1UF/10V

DC11 1

C

2

0.1UF/10V

DC12 1

2

0.1UF/10V

[6,18] [6,18]

M_CSA#1 M_ODTA0

[18] [18]

M_ODTB1 M_CSB#1

M_A_A14

M_B_A14

M_B_A4 M_B_A1 M_B_A10 M_B_A0

B

[10,18] M_B_BS0

M_B_A8 M_B_A5 M_B_A3

M_B_A9 [18]

M_CKEB1

[10,18] M_CKEB0 [10,18] M_B_BS2

[10,18] M_CSB#0 [10,18] M_ODTB0 [10,18] M_B_RAS# [10,18] M_B_BS1 [10,18] M_B_CAS# [10,18] M_B_W E#

A

M_B_A11 M_B_A6 M_B_A7 M_B_A12

M_B_A13 M_B_A2

47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm

5 6 4 4 1 2 3 3

12 11 13 13 16 15 14 14

DRN16E DRN16F RN0901D DRN10D DRN11A DRN16B DRN16C DRN11C

47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm

6 4 7 1 3 3 5 6

11 13 10 16 14 14 12 11

DRN17F DRN17D DRN15G DRN17A DRN17C DRN14C DRN14E DRN14F

47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm

8 7 2 7 8 4 6 1

9 10 15 10 9 13 11 16

DRN17H DRN14G DRN14B DRN17G DRN14H DRN14D DRN15F DRN14A

47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm 47Ohm

5 3 8 2 5 2 1 4

12 14 9 15 12 15 16 13

DRN15E DRN15C DRN15H DRN15B DRN17E DRN17B DRN15A DRN15D

DC13 1

2 B

0.1UF/10V

DC15 1

2

0.1UF/10V

DC17 1

2

0.1UF/10V

A

DC18 1

2

0.1UF/10V

Title DDR3 : termination

GND ASUSTeK COMPUTER INC. NB6 Size

5

4

3

2

Vincent Chung

Project Name

Custom Date:

Engineer:

Rev

G71V

1.0 Sheet

Monday, February 16, 2009 1

9

of

91

BYTE 1

A2 E2 R3 R7

BYTE 0

B7 A8 F7 E8

HYB18T512161B2F-25

M_B_BS0 M_B_BS1 M_B_BS2 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

B

BYTE 6

BYTE 7

BYTE 7 BYTE 6

M_B_DQ54 M_B_DQ50 M_B_DQ53 M_B_DQ52 M_B_DQ51 M_B_DQ48 M_B_DQ49 M_B_DQ55 M_B_DQ59 M_B_DQ56 M_B_DQ62 M_B_DQ61 M_B_DQ60 M_B_DQ63 M_B_DQ57 M_B_DQ58

K7 L7 K3 L8 R8 L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9

M_B_DQS7 M_B_DQS#7 M_B_DQS6 M_B_DQS#6

B7 A8 F7 E8

CK CK# CKE

BA0 BA1 NC/BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 LDQ0/DQ0 LDQ1/DQ1 LDQ2/DQ2 LDQ3/DQ3 LDQ4/DQ4 LDQ5/DQ5 LDQ6/DQ6 LDQ7/DQ7 UDQ0/DQ0 UDQ1/DQ1 UDQ2/DQ2 UDQ3/DQ3 UDQ4/DQ4 UDQ5/DQ5 UDQ6/DQ6 UDQ7/DQ7

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDL VDD1 VDD2 VDD3 VDD4 VDD5 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSDL VSS1 VSS2 VSS3 VSS4 VSS5 ODT

UDQS UDQS# LDQS LDQS#

NC1 NC2 NC3 NC4

B3 F3

M_B_DM7 M_B_DM6

J2

N_FBAVREF1

E9 G1 G3 G7 G9 A9 C1 C3 C7 C9

BYTE 7 BYTE 6 +1.8V

MB_CLK_DDR1 MB_CLK_DDR#1 M_CKEB0 M_B_RAS# M_B_CAS# M_B_WE# M_CSB#0 M_B_BS0 M_B_BS1 M_B_BS2 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

J1 A1 E1 J9 M9 R1 E7 F2 F8 H2 H8 A7 B2 B8 D2 D8

BYTE 4

J7 A3 J3 N1 P9 E3

GND

K9

M_ODTB0

A2 E2 R3 R7

BYTE 5

M_B_DQ33 M_B_DQ37 M_B_DQ38 M_B_DQ32 M_B_DQ36 M_B_DQ34 M_B_DQ39 M_B_DQ35 M_B_DQ47 M_B_DQ40 M_B_DQ43 M_B_DQ45 M_B_DQ44 M_B_DQ42 M_B_DQ41 M_B_DQ46 M_B_DQS5 M_B_DQS#5 M_B_DQS4 M_B_DQS#4

BYTE 5 BYTE 4

E7 F2 F8 H2 H8 A7 B2 B8 D2 D8

100Ohm 1% MB_CLK_DDR0 1 2

K7 L7 K3 L8 R8 L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 F7 E8

CK CK# CKE

UDM LDM VREF

RAS# CAS# WE# CS# NC/A13 BA0 BA1 NC/BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 LDQ0/DQ0 LDQ1/DQ1 LDQ2/DQ2 LDQ3/DQ3 LDQ4/DQ4 LDQ5/DQ5 LDQ6/DQ6 LDQ7/DQ7 UDQ0/DQ0 UDQ1/DQ1 UDQ2/DQ2 UDQ3/DQ3 UDQ4/DQ4 UDQ5/DQ5 UDQ6/DQ6 UDQ7/DQ7

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDL VDD1 VDD2 VDD3 VDD4 VDD5 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSDL VSS1 VSS2 VSS3 VSS4 VSS5 ODT

UDQS UDQS# LDQS LDQS#

NC1 NC2 NC3 NC4

2 1

1

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

MB_CLK_DDR#0

R338 @ 100Ohm 1% MB_CLK_DDR1 1 2

J7

MB_CLK_DDR#1

R339

A3 J3 N1 P9 E3

GND

K9

M_ODTB0

@

A2 E2 R3 R7

B3 F3 J2

M_B_DM5 M_B_DM4

BYTE 5 BYTE 4

N_FBAVREF1

E9 G1 G3 G7 G9 A9 C1 C3 C7 C9

+1.8V

J1 A1 E1 J9 M9 R1 E7 F2 F8 H2 H8 A7 B2 B8 D2 D8

M_B_BS0 M_B_BS1 M_B_BS2

[9,18] [9,18] [9,18] M_B_DM[0:7]

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_CSB#0 M_CSB#1 M_CKEB0 M_CKEB1

[9,18] [9,18]

M_ODTB0 M_ODTB1

[18] [18] [18] [18]

[18]

C

M_B_A[0:14]

[9,18] [9,18]

[18]

M_B_DQS#[0:7]

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 [9,18] [9,18]

[18]

M_B_DQS[0:7]

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

[9,18]

MB_CLK_DDR0 MB_CLK_DDR#0 MB_CLK_DDR1 MB_CLK_DDR#1

M_B_RAS# M_B_CAS# M_B_WE#

[9,18] [9,18] [9,18]

B

J7 +1.8V A3 J3 N1 P9 E3

GND

K9

M_ODTB0

C1022

C1021

1UF/6.3V

C1020

1UF/6.3V

C1019

1UF/6.3V

A2 E2 R3 R7

1UF/6.3V

GND +1.8V

HYB18T512161B2F-25 2

HYB18T512161B2F-25

J8 K8 K2

2

1 2 2 1

[18] M_B_DQ[0:63]

U7207 UDM LDM VREF

RAS# CAS# WE# CS# NC/A13

A1 E1 J9 M9 R1

2

M_B_RAS# M_B_CAS# M_B_WE# M_CSB#0

J8 K8 K2

NC1 NC2 NC3 NC4

J1

HYB18T512161B2F-25

U7208 MB_CLK_DDR1 MB_CLK_DDR#1 M_CKEB0

ODT UDQS UDQS# LDQS LDQS#

D

2

M_B_DQS1 M_B_DQS#1 M_B_DQS0 M_B_DQS#0

GND

1

M_ODTB0

VSS1 VSS2 VSS3 VSS4 VSS5

GND

C1001

1

0.1UF/10V

C1002 0.1UF/10V

C1032 1UF/6.3V

C1031 1UF/6.3V

C1030

C1029

1UF/6.3V

1UF/6.3V

C1028 1UF/6.3V

2

K9

BYTE 1

VSSDL

N_FBAVREF1

R1010 C1010 1KOhm 0.1UF/10V 1%

C1027 1UF/6.3V

1

GND

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

N_FBAVREF0

R1009 C1009 1KOhm 0.1UF/10V 1%

2

A3 J3 N1 P9 E3

LDQ0/DQ0 LDQ1/DQ1 LDQ2/DQ2 LDQ3/DQ3 LDQ4/DQ4 LDQ5/DQ5 LDQ6/DQ6 LDQ7/DQ7 UDQ0/DQ0 UDQ1/DQ1 UDQ2/DQ2 UDQ3/DQ3 UDQ4/DQ4 UDQ5/DQ5 UDQ6/DQ6 UDQ7/DQ7

+1.8V

R1006 1KOhm 1%

1

J7

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9

VDD1 VDD2 VDD3 VDD4 VDD5

E9 G1 G3 G7 G9 A9 C1 C3 C7 C9

R1005 1KOhm 1%

BYTE 1 BYTE 0

2

BYTE 0

M_B_DQ6 M_B_DQ7 M_B_DQ1 M_B_DQ0 M_B_DQ4 M_B_DQ2 M_B_DQ5 M_B_DQ3 M_B_DQ15 M_B_DQ13 M_B_DQ14 M_B_DQ8 M_B_DQ12 M_B_DQ10 M_B_DQ9 M_B_DQ11

VDDL

N_FBAVREF0

1

E7 F2 F8 H2 H8 A7 B2 B8 D2 D8

BA0 BA1 NC/BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10

M_B_DM1 M_B_DM0

J2

1

C

NC1 NC2 NC3 NC4

A1 E1 J9 M9 R1

VREF RAS# CAS# WE# CS# NC/A13

B3 F3

2

ODT UDQS UDQS# LDQS LDQS#

J1

L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2

UDM LDM

1

VSS1 VSS2 VSS3 VSS4 VSS5

M_B_BS0 M_B_BS1 M_B_BS2 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

K7 L7 K3 L8 R8

CK CK# CKE

2

VSSDL

M_B_RAS# M_B_CAS# M_B_WE# M_CSB#0

+1.8V

J8 K8 K2

1

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

MB_CLK_DDR0 MB_CLK_DDR#0 M_CKEB0

2

VDD1 VDD2 VDD3 VDD4 VDD5

E9 G1 G3 G7 G9 A9 C1 C3 C7 C9

BYTE 3 BYTE 2

1

B7 A8 F7 E8

LDQ0/DQ0 LDQ1/DQ1 LDQ2/DQ2 LDQ3/DQ3 LDQ4/DQ4 LDQ5/DQ5 LDQ6/DQ6 LDQ7/DQ7 UDQ0/DQ0 UDQ1/DQ1 UDQ2/DQ2 UDQ3/DQ3 UDQ4/DQ4 UDQ5/DQ5 UDQ6/DQ6 UDQ7/DQ7

VDDL

N_FBAVREF0

+1.8V

2

BYTE 3 BYTE 2

M_B_DQS3 M_B_DQS#3 M_B_DQS2 M_B_DQS#2

BA0 BA1 NC/BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10

M_B_DM3 M_B_DM2

J2

+1.8V

1

BYTE 3

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9

VREF RAS# CAS# WE# CS# NC/A13

B3 F3

2

BYTE 2

M_B_DQ23 M_B_DQ22 M_B_DQ17 M_B_DQ19 M_B_DQ20 M_B_DQ18 M_B_DQ16 M_B_DQ21 M_B_DQ26 M_B_DQ24 M_B_DQ27 M_B_DQ29 M_B_DQ28 M_B_DQ31 M_B_DQ25 M_B_DQ30

L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2

UDM LDM

1

M_B_BS0 M_B_BS1 M_B_BS2 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

D

K7 L7 K3 L8 R8

CK CK# CKE

2

M_B_RAS# M_B_CAS# M_B_WE# M_CSB#0

J8 K8 K2

1

MB_CLK_DDR0 MB_CLK_DDR#0 M_CKEB0

U7205

1

1

U7206

2

2

3

1

4

2

5

1UF/6.3V

1UF/6.3V

+1.8V

2

C1034

C1033 1UF/6.3V

1

1UF/6.3V

2

C1035

1

2

C1036

1

1UF/6.3V

2

C1037

1

1UF/6.3V

2

C1038

1

0.1UF/10V

2

C1004

1

1

0.1UF/10V

2

C1003

1

2

GND

A

A

GND



Title : Cantiga -- CPU (1) Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

10

of

91

5

4

3

2

1

D

D

C

C



Title : Cantiga-DDR3/PEG(2) Engineer: Size

Project Name

Rev

C B

Date:

1.0 Friday, February 13, 2009

Sheet

11

of

B

91

A

A

5

4

3

2

1

5

4

3

2

1

D

D

C

C

B

B

A

A



Title : Cantiga--DDR3 bus (3) Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

12

of

91

5

4

3

2

1

D

D

C

C

B

B

A

A



Title : Cantiga--POWER (4) Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

13

of

91

5

4

3

2

1

D

D

C

C

B

B

A

A



Title : Cantiga-POWER(5) Engineer: Size

Project Name

Rev

Custom Date: 5

4

3

2

1.0 Sheet

Friday, February 13, 2009 1

14

of

91

5

4

3

2

1

D

D

C

C

B

B

A

A



Title : Cantiga-GND Engineer: Size

Project Name

Rev

B Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

15

of

91

5

4

3

2

1

D

D

C

C

B

B

A

A



Title : Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

16

of

91

5

4

3

2

1

NU1A

[3] [3]

H_DSTBP#1 [3] H_DSTBN#1 [3] H_DINV#1 [3] H_DSTBP#2 [3] H_DSTBN#2 [3] H_DINV#2 [3] H_DSTBP#3 [3] H_DSTBN#3 [3] H_DINV#3 [3] H_RS#0 H_RS#1 H_RS#2

[3] [3] [3]

+VCCP_NB R309

1

+VCCP_NB

2 1KOhm

1%

CPU_BSEL2

2 1KOhm

1%

CPU_BSEL1

[3] [3] [3] [4] [3] [3] [3] [3] [3] [3]

@ R310

1

+VCCP_NB

@ R311

2 1KOhm

1

1%

@

CPU_BSEL0

NC pin

T1002

AE36 AK35

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

AC38 AA33 AC39 AC33 AC35 AD42 AD43 AE40 AL32 AD39 AD41 AB42 AD40 AC43 AE41

H_ADS# H_BNR# H_BR0# H_BR1# H_DBSY# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

1

[3] H_PROCHOT_S# [3,5] H_THRMTRIP# [3] H_FERR#

B

H_ADSTB#0 H_ADSTB#1

E41 AJ41 2 0Ohm AG43 AH40

R1019 1

F42 D42 F41

[3] CPU_BSEL2 [3] CPU_BSEL1 [3] CPU_BSEL0 H_RS#0 H_RS#1 H_RS#2

+VCCP_NB

+V_PLL_CPU 49.9Ohm 49.9Ohm

+VCCP_NB

49.9Ohm 49.9Ohm

2BCLK_VML_COMP_VDD 2BCLK_VML_COMP_GND

1 NR64 1 NR65 1 NR66 1 NR67

2 2

CPU_COMP_VCC CPU_COMP_GND

AC41 AB41 AC42 AG27 AH27 AG28 AH28 AM39 AM40 AM43 AM42

CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35#

FSB

CPU_ADSTB0# CPU_ADSTB1# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY#

CPU_BPRI# CPU_DEFER# BCLK_OUT_CPU_P BCLK_OUT_CPU_N

CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR#

BCLK_OUT_ITP_P BCLK_OUT_ITP_N BCLK_OUT_NB_P BCLK_OUT_NB_N

CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

BCLK_IN_N BCLK_IN_P

CPU_RS0# CPU_RS1# CPU_RS2#

CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_PWRGD CPU_RESET#

BCLK_VML_COMP_VDD BCLK_VML_COMP_GND

CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#

CPU_COMP_VCC CPU_COMP_GND

+VCCP_NB

R1001 1

R1002 H_CPURST#

2 200Ohm

1

2

+VCCP_NB

+VCCP_NB

R1003 1

R1004 H_NMI

2

1

150Ohm @

+VCCP_NB

1

H_INTR

+VCCP_NB

@ 2

2 150Ohm @

G70G R1.2 0725 DA-03609-001_v08 R1007

C

R1008 H_BR0#

1

62Ohm

2

H_FERR#

62Ohm

+VCCP_NB

+VCCP_NB @

R1017 1

R1018 2

H_BR1#

1

62Ohm

AA41 AA40

H_CPUSLP#

51Ohm @

@

H_DPRSTP#

2 220Ohm

H_BPRI# [3] H_DEFER# [3]

G42 G41

CLK_CPU_BCLK [3] CLK_CPU_BCLK# [3] C4621 CLK_XDP_BCLK [67] 15PF/50V CLK_XDP_BCLK# [67]

AL43 AL42 AL41 BCLK_FEEDBACK_P AK42 BCLK_FEEDBACK_N

C4622 15PF/50V

AK41 AJ40 @ AF41 AH39 AH42 AF42 AG41 AH41

H_A20M# H_IGNNE# H_INIT# H_INTR H_NMI H_SMI#

AH43 H38

H_PWRGD [3] H_CPURST# [3]

AM33 AN33 AM32 AG42 AN32

H_CPUSLP# [3] H_DPSLP# [3] H_DPWR# [3] H_STPCLK# [3] H_DPRSTP# [3,79]

C4617 15PF/50V

1

H_D#[63:0]

AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34 AL38 AL35 AN34 AR39 AN35

CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3#

+VCCP_NB

1

H_REQ#[4:0]

H_DSTBP#0 [3] H_DSTBN#0 [3] H_DINV#0 [3]

C

M39 M41 J41

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A#[35:3]

H_ADSTB#0 H_ADSTB#1

H_DSTBP#3 H_DSTBN#3 H_DINV#3

SEC 1 OF 11

CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2#

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

C4616 15PF/50V

2

H_D#[63:0]

N37 L36 N35

CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1#

Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43

2

H_REQ#[4:0]

W39 W37 V35

H_DSTBP#2 H_DSTBN#2 H_DINV#2

CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#

1

[3] [3]

H_DSTBP#1 H_DSTBN#1 H_DINV#1

D

CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0#

1

H_A#[35:3]

T40 U40 V41

B

near CPU @

2

[3]

H_DSTBP#0 H_DSTBN#0 H_DINV#0

2

D

@

near CPU

@

[3] [3] [3] [3] [3] [3]

+VCCP_NB

R1011 1

2

H_PWRGD

150Ohm @

MCP75

+VCCP_NB

0

BSEL1 1

BSEL0 1

200

800

0

1

0

266

1067

0

0

0

C1701 2.2UF/10V c0603

NL1701 2

120Ohm/100Mhz C1702 2.2UF/10V c0603

1

BSEL2

1

667

1

2

FSB

166

1

BCLK

2

A

15mA

2

+V_PLL_CPU

C1703 2.2UF/10V c0603

A



Title : Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

17

of

91

5

4

D

C

M_A_DM[0..7]

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_A[0:14]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

[6] [6] [6] [6]

M_CSA#0 M_CSA#1

[6,9] [6,9]

M_CKEA0 M_CKEA1

[6,9] [6,9]

M_ODTA0 M_ODTA1

NU1C

[6,8]

M_A_DQS#[0:7]

SEC 2 OF 11

[6,8]

[6,8,9]

MA_CLK_DDR0 MA_CLK_DDR#0 MA_CLK_DDR1 MA_CLK_DDR#1

SEC 3 OF 11 M_A_DQ63 M_A_DQ62 M_A_DQ61 M_A_DQ60 M_A_DQ59 M_A_DQ58 M_A_DQ57 M_A_DQ56 M_A_DQ55 M_A_DQ54 M_A_DQ53 M_A_DQ52 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ47 M_A_DQ46 M_A_DQ45 M_A_DQ44 M_A_DQ43 M_A_DQ42 M_A_DQ41 M_A_DQ40 M_A_DQ39 M_A_DQ38 M_A_DQ37 M_A_DQ36 M_A_DQ35 M_A_DQ34 M_A_DQ33 M_A_DQ32 M_A_DQ31 M_A_DQ30 M_A_DQ29 M_A_DQ28 M_A_DQ27 M_A_DQ26 M_A_DQ25 M_A_DQ24 M_A_DQ23 M_A_DQ22 M_A_DQ21 M_A_DQ20 M_A_DQ19 M_A_DQ18 M_A_DQ17 M_A_DQ16 M_A_DQ15 M_A_DQ14 M_A_DQ13 M_A_DQ12 M_A_DQ11 M_A_DQ10 M_A_DQ9 M_A_DQ8 M_A_DQ7 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ2 M_A_DQ1 M_A_DQ0

AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35

M_A_DM7 M_A_DM6 M_A_DM5 M_A_DM4 M_A_DM3 M_A_DM2 M_A_DM1 M_A_DM0

AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34

MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0

[10] M_B_DQ[0:63]

B

A

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_BS0 M_B_BS1 M_B_BS2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

[10] [10] [10] [10]

[9,10] [9]

M_CSB#0 M_CSB#1

[9,10] [9]

M_CKEB0 M_CKEB1

[9,10] [9]

M_ODTB0 M_ODTB1

[9,10] [9,10] [9,10] M_B_DM[0:7]

1

NU1B

[6,8]

M_A_DQS[0:7]

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

[6,9] [6,9]

[6,8,9] [6,8,9] [6,8,9]

2

[10]

MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0

MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N

M_A_DQS7 M_A_DQS#7 M_A_DQS6 M_A_DQS#6 M_A_DQS5 M_A_DQS#5 M_A_DQS4 M_A_DQS#4 M_A_DQS3 M_A_DQS#3 M_A_DQS2 M_A_DQS#2 M_A_DQS1 M_A_DQS#1 M_A_DQS0 M_A_DQS#0

AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

MEMORY PARTITION 0 MRAS0# MCAS0# MWE0# MBA0_2 MBA0_1 MBA0_0

MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0

MCLK0A_2_P MCLK0A_2_N MCLK0A_1_P MCLK0A_1_N MCLK0A_0_P MCLK0A_0_N MCS0A_1# MCS0A_0# MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0

AV17 AP17 AR17

M_A_RAS# M_A_CAS# M_A_WE# M_A_BS2 M_A_BS1 M_A_BS0

AP23 AP19 AW17

M_A_A14 M_A_A13 M_A_A12 M_A_A11 M_A_A10 M_A_A9 M_A_A8 M_A_A7 M_A_A6 M_A_A5 M_A_A4 M_A_A3 M_A_A2 M_A_A1 M_A_A0

AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19

AW33 AV33 BA24 AY24

MA_CLK_DDR1 MA_CLK_DDR#1

BB20 BC20

MA_CLK_DDR0 MA_CLK_DDR#0

AT15 AR18

M_CSA#1 M_CSA#0

AP15 AV15

M_ODTA1 M_ODTA0

AU23 AT23

M_CKEA1 M_CKEA0

[6,8,9] [6,8,9] [6,8,9]

M_B_DQ63 M_B_DQ62 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ58 M_B_DQ57 M_B_DQ56 M_B_DQ55 M_B_DQ54 M_B_DQ53 M_B_DQ52 M_B_DQ51 M_B_DQ50 M_B_DQ49 M_B_DQ48 M_B_DQ47 M_B_DQ46 M_B_DQ45 M_B_DQ44 M_B_DQ43 M_B_DQ42 M_B_DQ41 M_B_DQ40 M_B_DQ39 M_B_DQ38 M_B_DQ37 M_B_DQ36 M_B_DQ35 M_B_DQ34 M_B_DQ33 M_B_DQ32 M_B_DQ31 M_B_DQ30 M_B_DQ29 M_B_DQ28 M_B_DQ27 M_B_DQ26 M_B_DQ25 M_B_DQ24 M_B_DQ23 M_B_DQ22 M_B_DQ21 M_B_DQ20 M_B_DQ19 M_B_DQ18 M_B_DQ17 M_B_DQ16 M_B_DQ15 M_B_DQ14 M_B_DQ13 M_B_DQ12 M_B_DQ11 M_B_DQ10 M_B_DQ9 M_B_DQ8 M_B_DQ7 M_B_DQ6 M_B_DQ5 M_B_DQ4 M_B_DQ3 M_B_DQ2 M_B_DQ1 M_B_DQ0

AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5 BA8 BC8 BB4 BC4 BA7 AY8 BA9 BB10 BB12 AW12 BB8 BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42

M_B_DM7 M_B_DM6 M_B_DM5 M_B_DM4 M_B_DM3 M_B_DM2 M_B_DM1 M_B_DM0

AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42

MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0

MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N

M_B_DQS7 M_B_DQS#7 M_B_DQS6 M_B_DQS#6 M_B_DQS5 M_B_DQS#5 M_B_DQS4 M_B_DQS#4 M_B_DQS3 M_B_DQS#3 M_B_DQS2 M_B_DQS#2 M_B_DQS1 M_B_DQS#1 M_B_DQS0 M_B_DQS#0

AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

D

MEMORY PARTITION 1 MRAS1# MCAS1# MWE1# MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P MCLK1A_2_N

MEMORY CONTROL 1A

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

MEMORY CONTROL 0A

M_A_BS0 M_A_BS1 M_A_BS2

[6,8] M_A_DQ[0:63]

3

MCLK1A_1_P MCLK1A_1_N MCLK1A_0_P MCLK1A_0_N MCS1A_1# MCS1A_0# MODT1A_1 MODT1A_0 MCKE1A_1 MCKE1A_0

AW16 BA15 BA16

M_B_RAS# M_B_CAS# M_B_WE#

BB29 BB18 BB17

M_B_BS2 M_B_BS1 M_B_BS0

BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18

M_B_A14 M_B_A13 M_B_A12 M_B_A11 M_B_A10 M_B_A9 M_B_A8 M_B_A7 M_B_A6 M_B_A5 M_B_A4 M_B_A3 M_B_A2 M_B_A1 M_B_A0

[9,10] [9,10] [9,10]

C

BA42 BB42 BB22 BA22

MB_CLK_DDR1 MB_CLK_DDR#1

BA19 AY19

MB_CLK_DDR0 MB_CLK_DDR#0

BB14 BB16

M_CSB#1 M_CSB#0

BB13 AY15

M_ODTB1 M_ODTB0

AY31 BB30

M_CKEB1 M_CKEB0

MCP75 MCP75 M_B_DQS[0:7]

[10]

B

M_B_DQS#[0:7]

M_B_A[0:14]

[10]

[9,10]

A

MB_CLK_DDR0 MB_CLK_DDR#0 MB_CLK_DDR1 MB_CLK_DDR#1



Title : Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

18

of

91

5

4

3

2

1

D

D

NU1D

SEC 4 OF 11

+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL

MEM_COMP_GND

AM41

2

C

AN41

1

R1202 40.2Ohm

REF:DG-03328-001_V03

+VCCP_NB NL1702 2 1

1 2

2 B

C1704 2.2UF/10V c0603

1

120Ohm/100Mhz C1705 2.2UF/10V c0603

2

15mA 1

+V_PLL_XREF

C1706 2.2UF/10V c0603

AA22 AP12 G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9 BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11 T24 T26

AY32 +1.8V

MEM_COMP_VDD MEM_COMP_GND GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64

AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31

4.77A NC65 1UF/10V mb_c0603 /X/NB

C

NC60 1UF/10V mb_c0603 /X/NB

NC64 0.1UF/10V

1

1

MRESET0# MEM_COMP_VDD

BA30 BA31

+

GND GND GND 11G233310536030 11G233310536030

NC63 1UF/10V mb_c0603 /X/NB

GND 11G233310536030

GND

2

T27 U28 U27 T28

MCKE1B_0 MCKE1B_1

CE8605 220UF/2V ESR=15mOhm/Ir=2.7A

2

+V_PLL_XREF

R1201 40.2Ohm

MCKE0B_0 MCKE0B_1

2

AV23 AN25

AY16 BC13

1

M_CKEA2 M_CKEA3

MODT1B_0 MODT1B_1

2

[8,9] [8,9]

MODT0B_0 MODT0B_1

NC66 0.1UF/10V

1

AN17 AN15

BC16 BA13

1

M_ODTA2 M_ODTA3

MCS1B_0# MCS1B_1#

2

[8,9] [8,9]

MCS0B_0# MCS0B_1#

BA20 AY20

2

AU17 AR15

AY23 BA23

1

M_CSA#2 M_CSA#3

MCLK1B_0_P MCLK1B_0_N

1

[8,9] [8,9]

MCLK0B_0_P MCLK0B_0_N

BA41 BB41

2

BA21 BB21

MCLK1B_1_P MCLK1B_1_N

1

[8] MA_CLK_DDR2 [8] MA_CLK_DDR#2

MCLK1B_2_P MCLK1B_2_N

MCLK0B_1_P MCLK0B_1_N

MEMORY CONTROL 1B

BB24 BC24

2

+1.8V

[8] MA_CLK_DDR3 [8] MA_CLK_DDR#3

MCLK0B_2_P MCLK0B_2_N

MEMORY CONTROL 0B

AU33 AU34

NC67 0.1UF/10V

GND

B

T33 T34 T35 T37 T38 T7 T9 U18 U20 U22

MCP75

A

A



Title : Engineer: Size

Project Name

Rev

C Date: 5

4

3

2

1.0 Friday, February 13, 2009

Sheet 1

19

of

91

5

4

3

2

1

D

D

NU1E

H9 G9

[53] PCIE_RXP2_MINICARD [53] PCIE_RXN2_MINICARD

F9 E9 H7 G7 +VCCP_NB B

T17 W19 U17 V19 W16 W17 W18 U16

2

NC4

NC3

1UF/6.3V

1UF/6.3V

PEF_CLKREQ/GPIO_17# PEF_PRSNT/GPIO_47#

PE5_REFCLK_P PE5_REFCLK_N

PEG_CLKREQ/GPIO_18# PEG_PRSNT/GPIO_48#

PE6_REFCLK_P PE6_REFCLK_N

PE_WAKE#

PEX_RST0#

PE1_RX0_P PE1_RX0_N

PE1_TX0_P PE1_TX0_N

PE1_RX1_P PE1_RX1_N

PE1_TX1_P PE1_TX1_N

PE1_RX2_P PE1_RX2_N

PE1_TX2_P PE1_TX2_N

PE1_RX3_P PE1_RX3_N

PE1_TX3_P PE1_TX3_N

+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8

1

1

0.1UF/10V

2

NC69

0.1UF/10V

1

2

2

NC68

1

2

C1536 2.2UF/6.3V

1

430mA

PE4_REFCLK_P PE4_REFCLK_N

T19 U19

+DVDD1_PEX1 +DVDD1_PEX2

+VCCP_NB

1

NL1703 2

161mA

+V_PLL_PEX

T16

+V_PLL_PEX

C1534

2

1

1

C1535

4.7UF/6.3V

R1501