J

Phys.

© EDP DOT

Pr3-51

Les Ulis

10.1051/jp420020035

modeling and design

MOSFET

analog

parameter

for

extraction

low

temperature

circuit

P. Martin, M. CEA-LETI, National

CSEM,

~

(2002)

France12

IV

Sciencei,

Bucher~

and

C.

Enz~

17 rue des Madyrs, 38054 Grenoble cedex 9, France Technical University ofAthens, GR 15773 Zographou, 2007 Neuchdtel, Switzerland

Athens,

Greece

SPICE used1n infiaredlmage cooled parameters needed for simulation of CMOS readout circuits sensors temperature are extracted using a specific MOSFET model based on the EKV 2.6 compact clJarge model It is used below 200 K and is very well adapted to analog simulation weak and modemte it was m Inversion regimes successively applied on different CMOS different foundries. from The model's performance is processes Abstract:

at low

this work for a 0.35 pm bT~ single gate process Expmlrnental resuIt5 on the evolutJoJ~ of the low and the matching parameters between 300 K and 77 K are also presented Contrary to the transistor NMOS the threshold voltage differences of buried channel PMOS less sca~tered as the transistors, transistors are temperature is lowered The same trend with temperature is observed on the flicker noise parameter

demonstrated

&equeJ~cy

m

noise

1.INTRODUCTION needed for simulation and design of CMOS readout used in infrared focal circuits are (IRFPA) working at low (77 K) or at intermediate temperature (130 K, 200 K). As CMOS of MOSFET not provide them, fiJll sets parameters (DC, AC, I/f noise and matching parameters) must be extracted prior to circuit simulation using a MOSFET model placing special emphasis on the weak and moderate inversion regimes where most of the transistors of the IRCMOS readout circuits are operating. In this paper we use a specific model based on the EKV 2.6 compact charge model formalism collaboration with the EPFL modeling group [2]. It was [I] and developed in such different stabilized bulk [3], 0.5 successively applied on 0.7pm-5V CMOS processes as different model's foundnes. The with and without dual polysilicon gates, from and 0.35 pm-3.3V, performance is demonstrated in this paper for a 0.35 pm N~ gate technology. Experimental results on the evolution of the low %equency noise and transistor matching parameters down to 77 K for both NMOS and PMOS transistors also presented. are SPICE

parameters

plane

arrays foundries do

2.

THE

LOW

VERSION

TEMPERATURE

OF

THE

EKV

2.6

MODEL

standard EKV 2.6 model ii %om EPFL, as well as for most MOSFET models including BSIM3v3 of University of Califomia, Berkeley, is valid at or near room temperature. As soon as the temperature is electrical model is unable to reproduce accurately the experimental than 200K, the EKV2.6 lower modified model has then to be used due to physical phenomena specific to low characteristics. A

The

temperahtre. model incorporates a In particular this applicatton including Coulomb, phonon and saturation.

The

mobility law for

the

effective

new

surface vertical

charge-based mobility model for roughness scattering mechanisms field is given by:

low as

well

temperature as

velocity

JOURNAL

pr3-52

ECO, EPH, ESR,

layer

inversion

which

~ ( ~~ ~ (

~e~

ECO

EPH

ESR

is

adjustable parameters, and Ecn inversion charge Qt and of the

and PO are of the

~xi

li~nction

a

IV

~~~

~e~

~

where

PHYSIQUE

DE

~

E~~

In

~bl

]j+

=

electrical

the

vertical

bulk

charge Qbi

field in the

(2)

,

with q

1/2 for

=

The

along

manner.

the

channel

vertical

The

channel.

field

vta

dependent

effective

satwation

dependence

bias

for

mobility model. The implementation of this charge-based mobility reproduce very accurately the drain current as seen introduced

integration

is obtained

of velocity

effect

parameters

additional

No

PMOS.

whole

the

Therefore, the

channel.

field

and 1/3 for

mobility of

effective

along the the

NMOS

on

with

of the

above

mobility is also substrate

itself

introduced

drain

or

mobility law dependent on

local

mobility becomes

m

effects

a

need

similar

be

to

in the

Gm, which is the

transconductance

difficult

most

test

is a major improvement as it allows to Fig, I and Fig. 2. The fining of the gate for the mobility model in the ohmic mode, is also model in

presented. &Ew5

~/L-20@nv10@m

Vdw50mV

lVM

the bias and the on simulator However,

also

circuit

temperature

I) such that the weak inversion the ~NUO= I). This parameter temperature on illustrated in Fig. 5, but does not ai§ect the strong parameter

but

temperature

compact model

slope allows inversion

version may

geometry. It

be

cannot

approximation, as a of the EKV model by introducing a new its theoretical value depending only excess

minimising

the

first

inversion

weak

in

error

as

regime [4].

around 150K for NMOS transistors in this Another phenomenon which appears at temperatwes %eeze-out effect in the LDD This effect is also complex and is not taken technology is the corner zones. conductance of short into exists when evaluating the drain As a result, an transistors at low account. error (Fig. 6). However, this drain-to-source voltages (less than 250 mV) where this effect is the most severe phenomenon is no more of importance in saturation due to a field-assisted impurity ionisation effect as described in Ref. [5].

W~-10n0vd~s0mv

Wl-10t035vd,+mV

Mm~

~

iE~8

~

NUOWI

i 7

~ iE48

~

'

VW=3v

, '

~,,Mv

~~

M

1J3

MS

la

175

1

a

0 S

I

5

Figure

5

Bur~ed

channel transistors

freeze-out at

77 K.

2

2~

3

3 5

vw Ml

vw (v(

effects

1n

AMOS

Figure

6

Freeze-out

NMOS

effect transistor

LDD

1n

at

77 K

zones

for

a

short

JOURNAL

Pr3-54

charge-based

This

Mentor Graphics as implemented also optimisation.

noise

Flicker

compact

model is valid and

triode to satwation. It proprietary model using the

a

UTMOST~

Silvaco

the

m

FREQUENCY

LOW

3.

and still

and %om

inversion

strong

to

extracted

were

IV

continuous

implemented

was

User

Defined

software

used

all

in

device

simulator

circuit

(UDM/CMPI)

Model for

operating regions, %om weak

ELDO~

in the

interface.

%om It

was

extraction

parameters

and

PARAMETERS

NOISE

parameters

PHYSIQUE

DE

this technology at 77 K, 200 K and 300 K

on

using

the

following

model:

~~~

~~~

analog application, special emphasis

For

the

weak

moderate

and is

temperature

shown

with

decreases

7

extracting

on

of

evolution

The NMOS

transistors,

the AF

the

and KF

flicker

the

of

parameter

KF

noise parameters in parameter KF with

noise

flicker

noise

model

tested

also

was

300K

at

and

in

77 K

wide

a

covering weak, moderate and strong inversion regimes for both NMOS transistors (Fig. 8). We expenmentally found that a bener agreement with measurements obtained by modil§qng relation (3) according to: transconductance

s

where

EF

a

is

referred

gate

and

~ ~~

=

~~

of gate range and PMOS would

be

(~)

~ax ~fW ~W ~~~

process-dependent exponent,

not strictly equal to 2, and allowing to explain why the input voltage Sid / Gm~ is generally not bias-independent as pointed out by different authors references therein). The EF parameter values we for NMOS and PMOS transistors measure

noise

(Ret [6] and different

%om

transistors

PMOS

temperatwe.

preceding

The

Fig.

in

placed

was

regimes. Contrary to

inversion

~~~

~~~

~ax

altd

0.5

0.35

technologies

pm

at

low

temperature

or

at

temperature

room

lie

between

1.8

2.3.

lE.24

NMOS

f tE.32

iE.25

~

Z

~

3

PMOS

$

iF.26

~

100

50

Ftgure

7

Evolution

'50

200

Tempw«Wm

lx

of tile

flicker

300

L~6

t&08

t~07

t&06

tE~5

tE44

'E~3

tE42

Gm isl

parameter

noise

Figure 8. Test of tile flicker noise model (0 35 pm bT~ gate process, (Vds(=3 V, f=

KF

vntl1temperature

at

77 K

I Hz)

4.MATCHINGPARAMETERS

The

EKV 2.6

for

geometry-

model and

[I

as

well

as

bias-dependent

in

its

evolved

device-to-device

presented here, matching in statistical

version

has

a

circuit

ability to analysis using

built-in

account a

single

WOLTE 5

model

parameter

MOSFET The strtlctures

(W

set

type. Note that such

device

per

Pr3-55

feature

a

commonly available

is not

with

other

models.

matching parameters were containing a number of

extracted

on

modules

for

this

0.35

pm

and

NMOS

using

CMOS process PMOS transistors

with

dedicated

test

different

sizes

L=12.6x12.6,

12.6xl.75, 0.77x12.6, 1.75xl.75, 0.77x0.77 and 0A9x0.35 pm~) Each module has size, placed in line and spaced by 14 pm. The reported in this measurements same made by extracting the parameters in the linear mode. Measured matching parameters at paper were different factor (KP) and temperature for the threshold voltage (VTO), current substrate coefficient (GAMMA) using equation (5) %om Ref. 7 are given in Fig. 9, 10 and II. No variation of the mismatch x

transistors

21

of the

spacing (D) between pairs was experimentally found on such matching data at low temperature and their

with the

of the authors, in the

this

stabilized

evolution

process.

with

knowledge

To the

temperature

very

are

scarce

literature.

a~(AP)=

~~

+S( D~ (5)

3 IMOS t0

(

25

s

g

~

i

~~~~ ~'

,

lM

,

"'.

~~~

~

> ~

«

,

i

i

o

50

iM

100

250

200

300

50

150

100

Twn~ntorelK1

Figure

9

Evolution until

of tile AVTO

temperature

(Tox

200

Twnmawre

rr~smatch 7 5

Figwe

parameter

10.

EvolutJon

nm)

of tile AKP

until

250

300

[Xl

mismatch

parameter

temperature

7E43 6&03

(

NMOS 5&03 ~~~~

>

W03 3~03

$

m03 t&03 0E~0