Outline •

Introduction

•

Delay-Locked Loops

•

DLL Applications

•

Phase-Locked Loops – PLL overview – Building blocks: • VCO • PD • LF

– PLL analysis: • Linear • Nonlinear

– Simulation: • PFD PLL with Verilog • Bang-Bang PLL with MATLAB

•

PLL Applications

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Phase-Locked Loops

1

1

Why Phase-Locked Loops? Clock skew control and frequency multiplication Clock skew control and frequency multiplication

IC The PLL automatically nulls the phase and frequency difference between these two points

Ext. CLK

Clock pad

Int. CLK

4

Internal clock

Q

Output pad

PLL clock route Clock buffers and interconnects introduce delay

Frequency here 4 times the external clock frequency

External clock

Internal clock

Phase aligned

Output data

Output data registers delay [email protected]

Phase-Locked Loops

2

When discussing DLLs we have seen that those were devices sensitive to the phase of the input signal and that they could thus be used in phase control applications. PLLs are in some sense more sophisticated devices since they can be used to control not only phases but frequencies as well. In the example of the figure above, an application of a PLL similar to the one presented when introducing DLLs is depicted. You can imagine it as representing a microprocessor that runs with an internal clock frequency which is four times higher than the clock frequency of the external bus. The PLL inside the ASIC, is actually executing two roles at the same time: 1st it is ensuring that the internal and external clock phases are “the same” so that, for example, no setup or hold time violations occur and, 2nd that the internal clock frequency is an exact multiple (in this case four times) of the external bus clock frequency. If the frequencies were not exact multiples (even if the difference was extremely small) the internal and external clock phases would be constantly drifting from each other and synchronization related errors would occur periodically.

2

The Essence of a PLL Unlocked: Uncoordinated hands, gets nowhere

Locked: Finally learned, goes where he/she wants

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Phase-Locked Loops

3

3

PLL Block Diagram 1st order

Reference

Phase Detector

LF

Error Signal

Frequency Control

VCO

Out

f

Phase-Locked Loop functional blocks •

•

Phase Detector (PD): –

Voltage Controlled Oscillator (VCO): –

As the name indicates is an oscillator whose frequency is controlled by a voltage: fout = F(Vcontrol)

–

Sometimes the control quantity can be a current. In this case we have a Current Controlled Oscillator (CCO)

–

We will assume that the higher the voltage (or the current) the higher the frequency

–

Compares the phase of the reference signal to the VCO phase Depending on the type, produces an error signal: • •

–

•

Phase detectors can be also frequency sensitive; in this case they are called Phase-Frequency Detectors (PFD).

Loop filter (LF): – – –

Eliminates the high frequency components of the error signal Introduces a loop-stabilizing zero It can be implemented as: • • •

[email protected]

Proportional to the phase difference between the input and output phases; Gives just an indication on the sign of the phase error (bang-bang detector).

Phase-Locked Loops

An RC low-pass filter An active low-pass filter A charge-pump a resistor and a capacitor 4

If you have a close look at the block diagram of a Phase-Locked Loop (PLL) and compare it with that of a DLL you notice some similarities but as well some very fundamental differences: As the DLL, the PLL is a negative control loop that is sensitive to the phase of the reference signal and tries to null the phase difference between its input and its output. A major difference exists though, the PLL generates its own output signal while the DLL has as output a phase shifted version of the input signal. This ‘minor’ detail has very ‘dramatic’ consequences because the phase of the output signal can not be changed without changing the operation frequency of the VCO. In other words, the loop tries to adjust the operation frequency of the VCO in order to make its phase match that of the reference signal. If you recall that phase is the integral of frequency, then the VCO can be considered as an integrator introducing a pole in the transfer function. (Remember that, in the case of the DLL, the VCDL delay was directly set by its control voltage and thus the VCDL was not introducing a pole in the transfer function.) Because of the presence of the loop filter, the PLL is thus a second order system. Although second order systems are ‘basically’ stable (their phase never exceeds 180º and only in the case of lossless circuits the phase actually reaches 180º), they can have highly oscillatory transient responses. In real systems other poles will be unavoidably present and the PLL might become unstable. To avoid poor transient response and instability, the loop filter has thus to be made slightly more complicated than that of a DLL. Usually a PLL loop filter also introduces a zero in the transfer function to control the phase margin and thus the transient response and the loop stability. Finally, because the VCO might be initially operating at a frequency which is different from that of the reference signal, it is necessary that the phase detector will be also able to give an indication about the frequency error (or deviation). Basically all phase detectors are capable of providing a frequency error indication but this occurs only when the frequency of the reference signal and that of the VCO are extremely close. However, phase detectors that can detect a frequency difference under ‘any’ conditions also exist and these are called Phase Frequency Detectors (PFD)

4

PLL Basic Operation

err(t) in(t)- out(t) in(t)

Reference

err(t)>

out(t)

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

5

The detailed behavior of a PLL will depend on the type of phase detector and loop filter used in a particular implementation. However, the very basic operation can be discussed without going into the details of each building block. The picture above depicts in very general terms what happens at the main ‘nodes’ of a Phase-Locked Loop: The input signal and the VCO signals are compared by the phase detector. This device produces an output voltage that is proportional to the phase difference (error) between those two signals. The error signal is fed to a loop-filter that eliminates its high frequency components. At the output of the filter we have thus a signal that is an ‘average’ (not exactly, we will se later) of the phase error between the input and output phases. The filter output is then used to control the oscillation frequency of the VCO – ‘the loop is now closed’. If the error signal has the correct sign (and the loop is well designed) the VCO frequency and phase will converge to the input signal’s average frequency and phase. Like in the case of a DLL, it is easy to see that this is in fact a ‘standard’ control loop were the input variable is the phase of the input signal and the output variable is the phase of the VCO signal. All the well established control theory can be thus used to analyze the loop. Notice that the PLL output can be taken either at the loop-filter output or at the VCO output. This, of course, depends on the system application being considered. For example, in a clock recovery system the VCO signal is the desired output while in an FM demodulator the audio or the data signals are found straight after the loop-filter.

5

The VCO

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

6

Before going in any detail into the theory of operation of PLLs we will discuss its basic building blocks from the operation and circuit implementation points of view. This will allow to develop a practical knowledge of the circuits which will be later useful to understand the PLL theory. Some of the circuits that we discussed in the context of DLLs (for example the phase detectors) can be used as they have been described to implement PLLs. Some of others (for example the charge pump) might need a slightly different implementation to be used as a PLL building block. The only component that is really not ‘transposable’ to a PLL is the VCDL. Instead, in a PLL, a VCO is used. This component, as we have seen, marks the major difference between a DLL and a PLL. We will thus start by describing it.

6

Starved Inverter VCO The VCO is an oscillator • The oscillation frequency depends on the control voltage • It is usually modeled as: t

f (t )  K vco  Vcnt (t )  f 0

 (t )   f (t ) dt   0

Practical advice: • An odd-number of inverters is mandatory; • Always buffer the output signal; • Ensure a minimum oscillation frequency; • Preferably use a minimum of 3 inverters.

0

1  ( s )  K vco   Vcnt ( s ) s

Vdd

Ibias

Vcontrol

The VCO behaves as The VCO behaves as a phase integrator a phase integrator

out

Imin

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Phase-Locked Loops

7

Much of what we have learned about the starved inverter and the VCDL can be applied to a starved inverter VCO. The main difference is that its output signal is internally generated and not a delayed copy of the input signal as is the case for a VCDL. A VCO is thus an oscillator as its name clearly indicates. The oscillation frequency is, in first approximation, proportional to the current flowing in the starved inverters. In practice (as shown in the figure above) the frequency is controlled by the loop-filter output voltage. A transconductor and current mirrors are required to generate the starving currents. Although the frequency versus control-voltage relationship is nonlinear, when in lock, the control-voltage can be considered as a small signal and this relationship is usually taken as linear:

f ( t )  K vco  V cont (t )  f 0 The phase detector actually compares the phase of the VCO signal with that of the reference signal. It is thus more useful to write the above relation for the VCO phase: t

 (t )   f (t ) dt   0 0

That is, the VCO transfer function is that of an integrator:

1  ( s )  K vco   V cont ( s ) s As stressed before, the VCO introduces a pole at the origin which, together with loop-filter pole, makes the PLL a second order system. When implementing a VCO a few practical points should be kept in mind. 1st an odd number of starved inverters is required, otherwise a latch would result and no oscillation would be produced. 2nd a minimum oscillation frequency should be guaranteed by preventing the starved current from descending below Imin. 3rd always buffer the VCO signal to make the transfer characteristics independent of loading. 4th use at least 3 starved inverters to ensure that the phase around the loop will reach 180º, a condition necessary (but not sufficient) for oscillation.

7

Differential VCO cell Bias P

To other cells

Vdd

C gs , P ×2

×1

out-

I

×1

×1

×1 g m, p

out+



in+

Cgs, N  Cgs,P 

in-

g m, p

C gs , N

2×I

Vcontrol ×1

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×2

Phase-Locked Loops

To other cells

8

The starved inverter VCO has the disadvantage of being single ended and thus more prone to be disturbed by power supply or substrate noise. For that reason, most integrated VCOs use differential cells. A popular choice is illustrated in the picture above. It is commonly known as ‘delay cell with symmetrical loads’. Its delay, and thus the resulting operation frequency, is controlled by the transconductance of the diode connected P transistor, its gate capacitance and the gate capacitance of the N transistor of the following stage. Since the transconductance is a function of the drain current, the oscillation frequency can be controlled by controlling the bias current of the differential pair and its associated loads. With a modification of the bias circuit this cell renders well to the implementations of self biasing techniques that achieve operation rather insensitive to temperature, supply voltage and process parameters. For further information on this topic, please refer to: John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biasing Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, November 1996, pp. 1723-1732

8

VCO Transfer function VCO - Run: 18/09/2000 (Extraction model: close interconnect), Fit order = 3 3.5  =-1.5, T=125C, Vdd=2.25V

3

 =0, T=25C, Vdd=2.5V  =+1.5, T=-55 C, Vdd=2.75V

Frequency (GHz)

2.5

2

Target operation frequency: 800 MHz Kvco = -2.36 GHz/V

1.5

Kvco = -3.72 GHz/V

1

0.5

Kvco = -1.17 GHz/V 0 -1500

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-1400

-1300

-1200

-1100 -1000 Control voltage (mv)

Phase-Locked Loops

-900

-800

-700

-600

9

The figure above represents the frequency versus voltage transfer function of a VCO implemented in a 0.25 m CMOS technology. The circuit uses the topology just described but implements the complementary structure, that is, the role of the NMOS transistors is taken by the PMOS and vice versa. Notice that the control voltage is measured negative since, for this implementation, it is referenced to Vdd and not to ground. The curves represent simulations for three corners taking the layout parasitics into account. Shown are curves for, in one case, typical process parameters and typical operation conditions and two extreme cases where the process parameters are assumed to be ±1.5  away from the nominal and the operation conditions are taken at the extremes of the operation range. Notice that the transfer function is really nonlinear so that modeling the VCO by its gain (Kvco) and free running oscillation frequency (f0) is really an approximation. However, as can be seen from the picture the approximation is reasonable since in lock, the control voltage is not expected to vary much more than a few tens of V in the vicinity of the operating point. This picture also reveals that the VCO gain is expected to vary by a factor bigger than 3 for the span of corners considered. This certainly needs careful consideration during the design phase of the PLL.

9

LC VCO Vdd Voltage controlled capacitance Implemented with PMOS transistors Out-

f0 

1 2  L  Ceq

Out+ Frequency selective load

Vcontrol

L

Equivalent model

Ceq

-1/Gm

-Gm R Resistive losses

[F]

Compensates losses

PMOS Capacitor

7.00E-10

Q

L / Ceq R

6.00E-10 5.00E-10 4.00E-10

Ignore absolute value of the capacitance. Measurements made on a VERY BIG transistor to minimize experimental errors. [email protected]

3.00E-10 2.00E-10 1.00E-10

Measurement Simulation

0.00E+00 -2.5

-2

-1.5

-1

-0.5

0

0.5

Phase-Locked Loops

1

1.5

2

2.5

Vgs 10

Some applications, like for example RF transmission, require a spectral purity (low phase noise) from the oscillator that cannot be achieved with the two previous circuits. Better phase noise characteristics can be achieved with an LC tank oscillator. The circuit shown above consists of an LC tank driven by a negative transconductance. The LC tank is composed of an inductor and a capacitance formed by two PMOS transistors connected as voltage-controlled capacitors in parallel with the gate capacitance of the transconductor. The negative transconductance is implemented by a differential pair with its inputs ‘cross-connected’ to its outputs so that positive feedback occurs around the loop. Frequency control is achieved by varying the bias of the PMOS transistors. In the case shown in the figure, the PMOS transistors are biased in accumulation. Under such conditions the capacitance can typically be expected to change by a ratio of 3:1 when the control voltage is changed form 0 V to Vdd. The phase noise performance of the circuit is strongly related with the quality factor Q of the inductor, being the quality factor the ratio of the energy stored to the energy lost per unit of time. Energy loss occurs mainly in the inductor’s parasitic resistor which accounts for wire resistance, skin effect and, in silicon processes, dissipative losses in the substrate. In silicon CMOS processes it is difficult to manufacture inductors which have Qs higher than 8. If the ultimate in spectral purity is required it is then necessary to build the resonant LC tank out of discrete components external to the IC.

10

The Phase Detector

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

11

Two phase detectors have already been described in the context of DLLs: the XOR and the DFF. These devices can be used to implement PLLs and we will look again at the DFF in the context of a Bang-Bang PLL. Two other important types of phase detectors need to be considered when discussing PLLs, these are: the Analog Multiplier and the Phase-Frequency Detector.

11

The Analog Multiplier as a Phase Detector A  cos(  t ) A  cos(  t )  B  cos(  t   )

Same frequency

B  cos(  t   )



Phase difference

A B cos( )  cos(2    t   ) 2

DC term

Double-frequency term Function of the signals amplitudes!

Low pass filtering

 Vout  

A B cos( ) 2

100

Function of the phase difference

(A  B)/2 [%]

50

0

K PD 

Maximum for  = /2 Maximum for  = /2

-50

-100 -2



d A B  Vout    sin( ) 2 dt

-1 

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0  [rad]

1

2 Phase-Locked Loops

12

In applications such as RF transmission, PLLs have sine-wave inputs and VCOs which generate sine waves. For such a PLL the phase detector most commonly used is the Analogue Multiplier. If two sine waves are applied to such a phase detector its output is a voltage that has a DC component and a component at the double of the operating frequency. The DC component is actually a function of the phase difference between the two input signals. After low-pass filtering by the loop filter, only the DC component remains (see equations above). The DC term represents thus the phase error between the two signals. Notice that phase detector gain is actually a function of the phase offset between the two signals. It is zero at 0 and  and maximum at /2. Like for the XOR case, the a PLL built using an analog multiplier should be designed to lock to a phase difference of 90º. For such a phase detector the zero phase error condition corresponds thus to a 90º phase shift between the input signals. Because of this, the analogue multiplier is also known as a ‘quadrature’ phase detector.

12

Gilbert Cell as an Analog Multiplier

Id2

Id1

I d  I d1  I d 2  Valid for:

W2/L2

  Cox 2

2   Cox Vvco

2



I ss

 2

W1 W2   Vref  Vvco L1 L2

 1

Vvco W1/L1

Vref

Iss

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Phase-Locked Loops

13

A Gilbert cell can be used as an analogue multiplier. The equations above assume the devices working in saturation and were derived under the assumption of the validity of the square-law. The output of the multiplier is a differential output current Id = Id1 – Id2. For details see: D. Soo and R. Meyer, ‘A four-quadrant NMOS analog multiplier,’ IEEE Journal of SolidState Circuits, v. 17, n. 6, Dec 1982, pp: 1174 – 1178 S. Qin and R. Geiger, ‘±5-V CMOS Analog Multiplier,’ IEEE Journal of Solid-State Circuits, v. 22, n. 6, Dec 1987, pp: 1143 – 1146

13

Phase Frequency Detector VCO lags VCO lags ref 1

D

Q

late vco

ref RST

1

D

Q

late

early

vco RST

early 1 error 0

VCO leads VCO leads ref vco late

Phase error = late - early Pulse width: proportional to phase error Sign: > 0  VCO lags < 0  VCO leads

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early 0 error -1 Phase-Locked Loops

14

The Phase-Frequency-Detectors (PFD) is one of the most widely used types of phase detectors since it gives unambiguous frequency error information even when the VCO is operating at a frequency well away from the reference frequency. Although made out of digital building blocks, it provides not only information about the phase error sign but also about its magnitude. The PFD is composed of two DFFs both having the D input connected to logic ‘1’ and their clock inputs connected in one case to the reference and in the other to the VCO. When a positive edge occurs on the reference signal the logic ‘1’ is loaded in the FF and the ‘late’ signal activated. Similarly when a positive edge occurs on the VCO the ‘early’ signal is activated. Whenever both, the ‘late’ and the ‘early’ signals, are simultaneously active, both FFs are reset by the output of the AND port. Notice the signals ‘early’ and ‘late’ are only simultaneously active during a very short time interval, only just long enough to reset the two FFs. For this reason the PFD is also commonly known as the ‘Three State’ Phase Detector meaning that only three of the four possible states are really stable namely: either ‘early’ or ‘late’ active or both inactive. We will start by looking at its operation when the PLL is frequency-locked, that is, the reference and VCO frequencies are the same, but a phase error still exists between the reference and the VCO. In the picture above two cases are considered, either the VCO phase is late (VCO lags) or the VCO phase is early (VCO leads). As can be seen in the figures above, the phase error information is not contained in the ‘late’ or the ‘early’ signals alone but in a combination of both. The phase error signal is taken as the difference between the ‘late’ and the ‘early’ signals. If the sign is positive (late-early>0), then the VCO phase lags that of the reference and if the sign is negative the VCO phase leads the phase of the reference. From the pictures above, it should also be clear that the amount of time that the error signal is active, either positive or negative, is proportional to the phase error between the reference and the VCO. The phase frequency detector thus ‘measures’ the amount of phase error.

14

PFD: Frequency sensitivity VCO slow VCO slow ref vco late early 1 error 0 -1 VCO fast VCO fast ref vco late early 1 error 0 -1 [email protected]

Phase-Locked Loops

15

With the exception of the PFD now being discussed, all the other phase detectors presented so far are strictly speaking not sensitive to frequency. They can be used to acquire frequency-lock when part of a phase-locked loop but this frequency ‘sensitivity’ is a property of the full loop (not of the phase detector alone). The loop can acquire frequency lock for reference frequencies which are within a small frequency range around the free running frequency of the VCO. This frequency range is actually dependent on the loop bandwidth. On the contrary, the three-state phase detector is frequency sensitive even when operated standalone. The pictures above illustrate this fact. Consider first the case where the VCO oscillation frequency is low compared with that of the reference signal. As a consequence the rising edges of the reference signal are going to be more (or much more) frequent than those of the VCO and only the late signal is going to be activated (except of course during the reset phases and, perhaps, at beginning of operation). There is a clear and consistent ‘late’ indication whatever the frequency difference between VCO oscillation frequency and the reference frequency. This ‘late’ signal forces the LF output voltage to increase, increasing thus the VCO frequency. Similarly, when the VCO runs too fast only the early signal is activated (the same commentary as above applies here) and the LF voltage is forced to decrease, decreasing the VCO oscillation frequency. A PLL using a PFD does not require any lock-acquisition aid. This is not the case for the other phase detectors already presented. They will not be able to acquire lock if the frequency difference between the VCO free running frequency and that of the reference signal exceeds the loop bandwidth. It is interesting to note that for a PLL using a PFD, during the frequency acquisition phase the loop actually behaves as a first order system. This is so because during this phase the ‘phase detector’ is actually comparing frequencies and not phases.

15

PFD Characteristics

Verr Vdd -4

-2 2

4



-Vdd

vco

vco

Late = 0 Early = 1

ref

Late = 0 Early = 0

ref

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Late = 1 Early = 0

ref

vco

Phase-Locked Loops

16

The Phase Frequency Detector characteristics are displayed in the picture above. The phase detector has a linear range of ±2 around zero phase error, which is four times as much as the analogue multiplier and twice as much as a Bang-Bang phase detector (simple FF). The state diagram above describes the behavior of the phase detector and illustrates why the PFD is called a three-state phase detector or even sometimes a sequentiallogic phase detector.

16

The Loop Filter

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

17

We will need now to revisit the team of loop filters. You should remember that that the PLL is a second order system. We need thus, to introduce a zero in the open-loop transfer function to guaranty stability and to optimize the close loop transient response. The loop-filters discussed in the context of DLLs are not suitable since their transfer function only contains a pole and no zero.

17

Charge-Pump and RC Loop Filter

Loop Filter HLF(s)

LF transfer function:

reference

H (s)  R1

Vcontrol

Pole:

vco R2

1  s  R2  C 1  s  ( R1  R2 )  C

fp 

1 2  ( R1  R2 )  C

fz 

1 2  R2  C

Zero:

C

The pole and the zero are coupled

Finite DC gain (=1)  Frequency and phase lock can only be achieved at a cost of a phase offset! Finite DC gain (=1)  Frequency and phase lock can only be achieved at a cost of a phase offset!

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Phase-Locked Loops

18

The loop filter displayed in the figure has a pole and a zero at frequencies that are controlled by the values of the resistors ‘R1’ and ‘R2’ and the capacitance ‘C’. As can be seen from the above equations the pole and the zero positions cannot be set independently. This means that the ‘natural’ frequency and the ‘damping’ factor of the PLL cannot be optimized independently (the meaning of these two terms will become clear later). This filter is quite suitable to be used in a PLL that uses an analogue or XOR phase detector since for these devices the AC component of the phase error signal is at the double of the operation frequency and can thus be readily eliminated by the low pass filtering operation. The main disadvantage of this filter is, as it was already the case for the passive filters used in DLLs, its finite DC gain. This means that frequency and phase lock can only be achieved at the cost of a non-zero phase error. To improve on this, an active filter can be used but an even better solution is, again, the use of a charge pump with an RC network.

18

Active Filter: Charge-Pump + RC network err ,n (t ) 

err  late(t )  early (t ) 2

err ,n (t )   1,1 late

ref PFD vco

Vcontrol (t )  Vres (t )  Vcap (t )

early

Charge Pump

Vcontrol

t   1 Vcontrol (t )  I cp   R  err , n (t )   err , n (t ) dt   V0 C   0

R

Integral term controlled by ‘C’ Proportional term controlled by ‘R’

C

Current magnitude Icp affects both

Zero at:

Infinite gain at DC

H LF ( s )  I cp 

1 s  R C s C

fz 

1 2  R  C

Independent

Pole at the origin [email protected]

Phase-Locked Loops

19

A charge pump can be used with a series RC network to form a low-pass filter which has a pole at the origin and a zero at a frequency determined by the RC time constant. The fact that the filter has a pole at the origin means that it has infinite gain at DC. As a consequence phase and frequency lock can be achieved with zero phase error. Besides the advantage of zero phase error in steady state conditions, this arrangement has the advantage to control the position of the zero without affecting the position of the pole. This is clearly not the case for the simple RC filter. In the time domain this arrangement can be seen as a proportional term controlled by the resistor value and an integral term controlled by the capacitor value (both being affected by the charge pump current).

19

Charge Pump Implementation Vdd M2

late

late

M6

M4

late

late Vcontrol

early early

M5

M3

early Icp

[email protected]

M1

Phase-Locked Loops

early R C

20

A slightly different implementation of the charge pump is necessary to work with a Three-State phase-detector. The circuit presented before had only two possible states, either sourcing or sinking charge to/from the loop capacitor. To be used with a PFD an extra state is required in which the charge pump neither sources nor sinks current to the filter network. One possible implementation is shown in the figure above. It is quite similar to the previous circuit but now there are four switching transistors (M3, M4, M5 and M6) and an OPAMP to prevent charge sharing. Transistor M4 is the current source switch (closed when late is active) and M3 is the current sink transistor (closed when early is active). When both late and early are inactive the charge-pump output is in a high impedance state where current is neither sourced/sank to/from the filter network. During such a state the control voltage is maintained constant in the capacitor. The OPAMP and transistors M5 and M6 prevent charge sharing. Suppose that this components were not present and consider for example one of the two possible cases in which early=0. In the absence of those components the parasitic capacitance present at the M1 drain node would discharge. Next time M3 would close, the voltage difference between this parasitic capacitance and the filter capacitor would result in charge sharing. The filter capacitance would thus share its charge with the parasitic capacitance with a consequent drop in voltage in a somehow ‘uncontrolled’ fashion. To prevent charge sharing it is enough to guaranty that the parasitic capacitances in the drain nodes of M1 and M2 have a voltage that is always equal (or very close) to the filter capacitor voltage. This is the role of the OPAMP connected as a voltage follower and the transistors M5 and M6. The OPAMP tracks the output voltage and M5 and M6 transistors switch states are always opposite to those of M3 and M5 respectively. This means that the drains of M1 and M2 are at all times connected either to the output voltage or to a replica of this voltage (the OPAMP output). The voltages being the same charge sharing will not occur.

20

Charge Pump Operation ref

vco

t1 late

t 2 early

Vcontrol

VI 

I cp

 t1 C VP  R  I cp

VP   R  I cp VI  

I cp C

 t 2

t [email protected]

Phase-Locked Loops

21

(Continued from the previous page) Notice that during the reset phase actually both M4 and M3 conduct for a brief instant requiring perfect charge-pump balance for zero net charge injection during the PD reset phase. For small phase errors the duration of the reset pulse might be identical or even smaller than the phase (delay) error, which might result in metastable operation of the PD. In this case, the charge sourced and sank to and from the load might be substantially wrong. To tackle this problem two approaches have been used. One is to specially design the PD so that the metastable operation is avoided all together even in the presence of short pulses. This however requires the chargepump to handle very short pulses and might result in a phase ‘dead band’ if not “perfectly” done. V. von Kaenel, D. Aebischer, C. Piguet, E. Dijkstra , ‘A 320 MHz, 1.5 [email protected] V CMOS PLL for microprocessor clock generation,’ IEEE Journal of Solid-State Circuits, v. 31, n. 11, Nov. 1996, pp: 1715 – 1722 A second approach, to avoid metastability, consists in artificially extend the reset pulse (for example by using a slow AND gate) and making sure that the source and the current sink are well matched so that both currents cancel. This second approach reduces (by the same amount) the phase range of the phase detector (not very critical for the three-state phase detector since its range around lock extends to ±2). M. Soyuer and R. Meyer, ‘Frequency Limitations of a Conventional Phase-Frequency Detector,’ IEEE Journal of Solid-State Circuits, v. 25, n. 4, Aug. 1990, pp: 1019 – 1022 (On this page) The picture above represents the main charge-pump signals in a PLL during lock acquisition. Don’t take this figure too seriously, although it is qualitatively correct, the relative frequency changes are exaggerated and the ratio between the proportional and integral terms are ‘untypical’. Usually the voltage changes due to the proportional term are much bigger than those due to the integral term. As shown in the picture, the proportional term generates a jump in the VCO control voltage when the ‘late’ or ‘early’ signals are activated. The jump is positive when the ‘late’ signal is activated and negative in the ‘early’ case, reflecting the sign of the phase error detected. Upon the reset phase, a voltage jump in the opposite direction occurs. Besides this proportional jump, a voltage change due to the integration of phase error also occurs. This voltage change is a ramp with final magnitude proportional the phase error and its sign depends of course on the sign of the phase error. Notice that since the VCO is a frequency integrator, the VCO phase is actually a ‘scaled’ version of the time integral of the control voltage.

21

The PLL

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

[email protected]

Phase-Locked Loops

22

The building blocks of a PLL have now been described. We looked only at few of the possible topologies. For each PLL element there are many possible implementations. The choice of which one to use depends strongly on the application being considered and on the technology selected for the implementation (discrete/integrated implementation, bipolar or CMOS technology). A good source of inspiration is no doubt the IEEE journal of solid-state circuits. Many of the most significant papers on PLLs (from 1953 to 2003) have been collected in the following books: “Monolithic Phase-Locked Loops and Clock Recovery Circuits Theory and Design,” Edited by Behzad Razavi, IEEE Press, 1996, ISBN 0-7803-1149-3 “Phase-Locking in High-Performance Systems From Devices to Architectures,” Edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7 Nowadays, even FPGAs offer integrated PLLs as circuit building blocks. It is thus necessary, even for the FPGA digital designer, to understand the basic principles (although in general terms) of PLL operation. In what follows we will look at the high level modeling of a PLL. As for the individual components, there are several possible topologies to be considered mainly depending on the type of phase detector and loop filter to be used. We will look only at two cases. In both cases a charge pump with an RC network will be used as a loop filter and the phase detectors to be analyzed are the Phase-Frequency Detector and the D Flip Flop (bang-bang loop).

22

Charge-Pump PLL with PFD Assume the PLL is locked in = out:

Phase error

‘ON’ time for either ‘Late’ or ‘Early’

ton 

err in

Q  I cp

err ( s)  in ( s )  out ( s)

Lumped contributions of: • Phase-Frequency Detector • Charge-Pump • Filter impedance

Average current in one cycle

err in

id  I cp

err 2

Vcnt ( s )  I cp 

The charge delivered in one cycle is proportional to the phase error err VCO phase

in , in

out , out late

in PFD

early

Charge Pump

±Icp

Vcnt

C

Z

err ( s)  Z (s) 2

[2]

Kvco in rad/(s.V)

K out ( s )  vco  Vcnt ( s ) s

[3]

[1] [2] [3]

VCO

R

[1]

K vco  I cp  Z ( s ) out ( s)  H (s)  in ( s ) 2  s  K vco  I cp  Z ( s )

[4]

err = in - out

[email protected]

Phase-Locked Loops

23

A PLL with a PFD it is strictly speaking a discrete-time (sampled) and nonlinear device. The model presented here is a continuous and linear approximation to the true behavior of the loop. The approximation is a good one if the loop bandwidth is at least 10 times lower than the frequency of the input. Under these conditions the PLL state changes very slowly and the average, instead of the detailed behavior, can be considered. To derive the transfer function of the PLL it is assumed that the PLL is locked so that the phase detector is operating in its linear range. To follow the steps highlighted above, we just need to remember the main points about the individual PLL components that we have discussed so far: 1st The phase detector measures the phase error between the input (reference) and the output (VCO) phases. The phase error results (at the output of the phase-frequency detector) in an ‘early’ or ‘late’ pulse of time duration equal to the phase error. 2nd The charge-pump uses the PFD output and injects, in a given cycle, a charge into the filter impedance that it is proportional to the phase error during that cycle. 3rd The charge pump current is then converted into a control voltage by the filter impedance. We have thus a voltage that is a scaled version of the phase error but which is as well transformed by the impedance characteristics. 4th The VCO uses the control voltage to produce the output phase which is then fedback to the phase detector (don’t forget the VCO introduces an integration ‘1/s’). Working around the loop the transfer function is obtained. The theory of charge-pump phase locked loops is described in detail in the classical paper (highly recommended reading): F. M. Gardner, ‘Charge-Pump Phase-Lock Loops,’ IEEE Transactions communications, vol. COM-28, no.11, November 1980, pp. 1849 - 1858.

on

23

A Second Order System Z (s)  R 

1 s C

[4] [5]

[5]

H ( s) 

I cp  (1  R  C  s)  K vco 2  C  s 2  I cp  (1  R  C  s )  K vco

A zero appears in the transfer function: It is used to compensate the PLL response

[6] can be put in the form:

H ( s) 

(1   z  s ) 2   s2   s 1 2

1

Compensating zero time constant

 z  R C n 

I cp  K vco

[email protected]

Natural frequency

2  C

R C  n 2

K  2    n 

[7]

n

n

The loop is second order



[6]

Damping factor

R  I cp  K vco 2

Any two of these parameters define the linearized, time-averaged behavior of the PLL

Loop gain

Phase-Locked Loops

24

If now the expression for the filter impedance is replaced in equation [4] we obtain the PLL closed-loop transfer function as function of the circuit parameters. It can be seen from equation [6] that the PLL is indeed a second order system. H(s) has a zero due to the presence of the resistor in the filter network. The position of this zero must be chosen to prevent excessive ringing in the transient response or even instability in real systems where additional poles might be present due to parasitics or intentionally placed poles. Equation [7] is equivalent to [6] but it is written, as it is common practice for second order systems, in terms of the natural frequency n and the damping factor ξ. These two parameters completely define the PLL behavior (more parameters are defined in the picture above but they are interrelated, once two are fixed the others will follow).

24

PLL Stability Open-loop transfer function:

H O ( s) 

I cp 1  s   z K vco   s C s 2

log |HO(s)|

H O ( s) 

I cp K vco  2 s 2  C

H O ( s)  For acceptable phase margin Place the zero 1/z well below n n cross over frequency of HO(s) if no zero was present)

0

1

z

n

Increasing K

(Slope = -2)

I cp  z K vco   2 C s

(Slope = -1)

log 

C

Im Two poles Re

K  2    n 

[email protected]

Phase-Locked Loops

R  I cp  K vco 2

25

The stabilizing zero is required to compensate for the negative phase shift introduced by the charge-pump loop-filter (integrator) and the VCO (an integrator as well). The zero must be placed well below n to obtain an acceptable phase margin. Notice that n would be the crossover frequency of the open loop transfer function if the zero would not be present (that is R = 0). The root-locus diagram plotted above represents the poles and zero locations for increasing values of the loop gain K = 2×ξ×n (increasing direction indicated by the curved arrows). As the magnitude of HO(s) increases (by increasing Icp, R and Kvco) the loop becomes progressively better damped because an increase in n allows more of the zero’s positive phase shift to offset the negative phase shift of the poles. For very large loop gain, one of the closed loop poles ends up at nearly the frequency of the zero and the other moves towards infinity. For a fixed n reducing the zero’s frequency improves the damping of the PLL, thus the bandwidth and stability can be adjusted while preserving a zero steady-state phase error. Notice that the loop transmission is equal to the open-loop transfer function HO(s) in the case described so far since the feedback factor (f) is 1, that is, the VCO output is feed directly to the phase detector output. However, if a frequency divider (counter) would be included in the feedback path then the loop transmission (f×HO(s)) and not the open transfer function HO(s) would have to be considered.

25

Jitter Peaking

log |H(s)|

Low damping ratio High damping ratio

H (s) 

(1   z  s ) 2   s2   s 1 2

1

n

0

n

log 

1 z

Over a given band of frequencies, H(s) will exceed unity. Jitter frequencies within this band will be amplified

For large damping ratios the zero frequency is below the closed-loop poles

To minimize jitter peaking keep the first closed-loop To minimize jitter peaking keep the first closed-loop pole next to the zero by using high loop gains pole next to the zero by using high loop gains

[email protected]

Phase-Locked Loops

26

At large damping ratios, in the root-locus diagram, the zero is to the right (lower frequency) of the closed-loop poles. As represented in the picture above, H(s) starts to rise at 1/z, then flattens due to the first pole and finally starts to decrease thanks to the second pole. This means that the closed-loop transfer function, after the zero’s frequency, exceeds unity until the zero’s effect is canceled by the poles. As a consequence any modulation on the input with spectral components within that band, will appear in the output amplified. To reduce peaking and/or the width of this frequency band it is thus necessary to keep the first pole as close as possible to the zero. This can be achieved by using large damping ratios.

26

Charge-Pump PLL with DFF Phase Detector Bang-bang (proportional) branch

fdiv, div ÷M

fdiv, div D

Q

early / late

Kbb

Vpd

ref

VCO Charge Vcnt Pump

Kvco

Phase detector: only early/late information

Integral branch

 ( )dt div ref early late

The VCO frequency is a function of the integral and proportional control paths:

1 f (t )  K bb  V pd (t )  K vco  Vcnt (t )  f 0 2 1  f (t )  K vco      V pd (t )  Vcnt (t )   f 0 2 

 [email protected]

K bb K vco

Phase-Locked Loops

27

A charge pump PLL is represented in the picture above. It consists of a DFF phase detector, a charge-pump with its associated capacitor, a VCO with two control ports and a clock divider. The DFF phase detector, as we have seen before when discussing DLLs, can only provide early/late phase information. The reference signal samples the PLL output and decides if the PLL phase is early or late. The phase detector then provides two control paths to the VCO. One of these paths (the proportional branch) is fed directly to the VCO and the other (the integral branch) is made through the charge pump and capacitor. Note that the VCO is represented as having two frequency control inputs with gains Kbb and Kvco. This can be actually the case or not depending on the implementation. If two independent control inputs (with different gains) are not available, the two control voltages can be summed before they are fed to the VCO (this is represented by the ‘different’ writing of the VCO frequency equation). The VCO output is finally fed back to the phase-detector through a clock divider which divides the VCO frequency by a factor M. The Bang-Bang is a non-linear system that cannot be accurately modeled by a linear approximation. An approach similar to the one made for the PFD is thus not possible. However, as in the case of a DLL using a DFF phase detector, expressions for tracking jitter can be readily obtained. A detailed explanation of the Bang-Bang PLL operation can be found in: R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” in “Phase-Locking in High-Performance Systems From Devices to Architectures,” Edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7 Or alternatively see: http://www.omnisterra.com/walker/index.html

27

Steady State Operation fdiv

Phase tracking ÷M

D

Q

Kbb

Vpd

early / late

ref

VCO

fref

Charge Vcnt Pump

The loops are non-interacting: • Bang-bang branch • Integral branch

 phase tracking loop (binary control)

Frequency tracking

 frequency tracking

In steady state conditions:

f [Hz]

• VCO frequency switched between two discrete frequencies (proportional branch) • Phase ramps up and down tracking the incoming phase (proportional branch)

fdiv

fref

• The integrator follows the ‘DC’ component of the phase detector, tracking the average frequency. [email protected]

Kvco

Phase-Locked Loops

t 28

The bang-bang PLL steady state operation can be summarized as follows: By definition, when in lock, the average frequency at the output of the clock divider is the same as that of the reference signal. However, due to the quantized nature of the phasedetector decision and the presence of the proportional branch, the VCO frequency is constantly switching between two discrete frequencies which, after division (M), are always slightly below or slightly above that of the reference signal. This causes the clock divider phase to ramp up and down around the reference signal phase, keeping track of it. For every transition of the reference clock, the phase detector makes a new decision. Ideally, early/late state should alternate at every decision. This represents a high frequency, well above the integrator bandwidth. Thus the integrator output just follows the long term unbalance between the early and the late decisions. The role of the integral branch is thus to set the center frequency of the VCO so that the reference frequency always falls within the two discrete frequencies at the output of the clock divider. The integral branch adjustment occurs so slowly so that it does not affect the operation of the high frequency branch (bang-bang) of the loop. The two loops can thus be considered non-interacting.

28

Proportional Branch fdiv

f [Hz]

Tracking Jitter Tracking Jitter Ref

2  Fstep

fref

VCO

Divider t t’

t Assuming lock Negligible fint over a cycle

1 Fstep    K bb  V 2

Peak-to-Peak phase detector voltage

Jbb=t’-t Assuming that: • Most decisions alternate state • Occasionally two consecutive decisions with no state change occur

J bb  

Fstep

1      K vco  V 2

J bb  

Kvco and Kbb in Hz/V

2  M  Fstep f vco

[1]

2

M    K vco  V f vco

2

[2]

f vco  M  f ref (in lock) 2

Design equation [email protected]

Phase-Locked Loops

Fstep 

f vco  J bb 2M

[3] 29

The bang-bang tracking jitter can be calculated under the assumption that at almost every decision the phase detector will alternate state, resulting in a very close to 50% duty-cycle. Occasionally, the same decision will be maintained during two consecutive clock cycles to compensate perhaps for charge pump unbalance or leakage. This results, of course, in two consecutive cycles having a consistently higher or lower frequency that the reference signal. Assuming this to be a worst case condition the tracking jitter can be easily derived and the result is presented above (equations [1] and [2]). Basically the tracking jitter is inversely proportional to the VCO frequency and proportional to the proportional gain (Kbb) and the frequency division factor. Most often we are interested in determining what should be the allowed frequency step due to the bang-bang loop to achieve a given jitter target. Rewriting equation [1] as in [3] we can determine Fstep. Example: suppose you are targeting a tracking jitter of 5 ps PP for a 4 times clock multiplier whose reference frequency is 40 MHz (fvco = 160 MHz). This requires the VCO frequency step not to exceed 16 KHz. (Special techniques are required to achieve such a small fractional change of the VCO frequency).

29

Integral Branch For the PLL to be stable the integral and the For the PLL to be stable the integral and the bang-band loops must be non-interacting bang-band loops must be non-interacting

‘Integral Branch Jitter’ ‘Integral Branch Jitter’

Phase increment during t = Tref

Ref

 (t )  bb (t )  int (t )

VCO

Integral contribution Divider

Bang-bang contribution Jint

For the loops to be non-interacting:

Vcnt

bb (t )  int (t ) The integral control voltage ramps up or down in between two phase detector decisions

J int 

I cp C

 K vco 

Stability criteria Stability criteria

M3 f vco



3

C V bb 1 K bb    f vco   1 I cp int M K vco

J int  J bb Necessarily [email protected]

Phase-Locked Loops

30

Between two phase decisions the voltage in the filter capacitor ramps down or up causing the frequency of the VCO to change very slightly during a reference clock period. This adds a small amount of jitter on top of the already discussed tracking jitter. This jitter can be easily calculated by integrating the frequency change (proportional to the integral control voltage change) over a reference period. The result is given above. It remains finally to discuss the problem of the PLL stability. For the loop to be stable, the integral and bang-bang loops must be non-interacting. This happens if within a reference period the phase walk-off (bb) contributed by the bang-bang branch will dominate over the phase walk-off (int) contributed by the integral branch. That is the ratio of these two quantities (ξ) must be bigger than 1 for stability. If ξ becomes significantly less than 1, the bang-bang portion of the loop will no longer stabilize the PLL and large low frequency oscillations will occur. Example: Lets consider a PLL that will lock to a 40 MHz reference and uses a voltage controlled crystal oscillator with gain Kvco = 14 kHz/V. The charge-pump current is 5 A and the filter capacitor 125 pF. From this will result an integral jitter of 0.044 ps. The VCXO has a ‘bang-bang’ control input that allows the frequency to be tuned of ±(1.75 kHz)/2. This results on a tracking jitter of 0.55 ps. Finally for this PLL ξ=250.

30

PLL Simulation

err

t

[email protected]

Phase-Locked Loops

31

Study of the behavior of a PLL might require up to milliseconds of PLL time simulation for VCO operation frequencies that might be small fractions of a nanosecond or even of the order of picoseconds. Attempting such a simulation at the circuit level (SPICE simulation) will simply not work, the simulation will be exceedingly slow. Moreover, behavioral simulation should be done early in the design phase to guide the circuit design phase and not the other way around. In what follows we will present a brief introduction to the behavioral level (system level) simulation of phase-locked loops. In one case Verilog, a hardware description language for digital circuits, will be used to detail the modeling of a Charge-Pump PLL with a phase frequency detector. In a second case a Bang-Bang PLL will be modeled. The procedures are of course general and are not exclusive to a specific programming language. SPICE simulations are nonetheless necessary to verify the actual circuit behavior. This will be however limited to simulate a few clock cycles of operation in some limiting cases just to confirm that the general term behavior is obtained from the circuit.

31

PLL Modeling with Verilog Verilog  Hardware description language for digital circuits Used for: • Hardware description • Hardware simulation • Source code for logic compilers reference

r

u

v

d

(digital)

Charge-Pump and Loop-Filter

VCO delay controlled by a 32 bit number to match the analogue precision

32

(analogue + digital)

VCO (digital)

÷M (digital)

Analogue is modeled inside with real variables

Algorithm: • Slice the time in very thin intervals (much smaller than Tvco) • Make the time advance in these time increments • At every time increment do: • Update the phase detector outputs • Calculate the new filter voltage according to the phase detector state • Update the VCO frequency as function of the filter voltage [email protected]

Phase-Locked Loops

32

Lets consider the use of Verilog to model a PLL with a three-state phase detector and a charge-pump. Verilog is a hardware description language developed to model and describe digital circuits. Verilog is also a simulation language that can be used to produce source code to synthesize logic circuits. The language is not targeted at modeling analogue circuits but it is possible, to some extent, to go around its ‘weakness’ in the analog domain. The idea is to use real variables to represent the ‘analogue’ voltages of a PLL. Real variables cannot be passed between modules so for example, in the block diagram above, the VCO is represented by a 32 bit number. All the ‘analogue’ computations happen inside the charge-pump and loop-filter block. In simple terms, Verilog is an event driven simulator, that is, events generate other events that are scheduled to happen at a given time. The Verilog engine advances time and executes at every instant the scheduled events and schedules new events to occur at a later time. The idea behind the PLL simulation with Verilog is to control the time advancement (automatically done by Verilog) so that it happens in small time steps of known duration. If that is the case, then the increment of the VCO control voltage can be calculated as function of the phase detector state. For example, recall that for the charge-pump filter with an RC, the integral term behaves like a ramp while the proportional appears like a voltage jump on the control voltage (with a bit more complexity other types of filter impedances can be modeled as well). This behavior is quite easy to model and thus to predict what is going to be the value of the control voltage at a given time. It should be clear that, higher accuracy is obtained for finer time increments. The simulation accuracy thus trades off against computation time. In any case, such simulations out perform transistor level SPICE simulations easily allowing to simulate the full process of lock acquisition.

32

Phase Detector and VCO Phase Frequency Detector `timescale 1 fs / 1 fs module ThreeStatePD (down, up, r, v); output

input

down, up;

// Early signal // Late signal

r, v;

// Reference input // VCO input

wire

r, v, reset;

reg

up, down;

initial

begin up = 0; down = 0; end

always @ (posedge r) up