Outline •
Introduction
•
Delay-Locked Loops – DLL overview – CMOS, refreshing your memory – Building blocks: • VCDL • PD • LF
– DLL analysis: • Linear • Nonlinear
– Lock acquisition – Charge sharing
•
DLL Applications
•
Phase-Locked Loops
•
PLL Applications
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Delay-Locked Loops
1
Clock skew control Clock skew control
Why Delay-Locked Loops?
IC Int. CLK
Ext. CLK
Clock pad
The DLL automatically nulls the skew between these two points
Q
Output pad
DLL clock route Clock buffers and interconnects introduce delay DLL delay + Clock buffers + Clock route delay = Clock period
External clock Phases 0 and 2π are indistinguishable
Internal clock
Phase aligned
Output data
Output data registers delay
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Delay-Locked Loops
2
DLL Block Diagram
1st order
Delay-Locked Loop functional blocks •
Voltage Controlled Delay Line (VCDL): –
Takes the reference clock as an input and delays it by some amount D.
–
The delay D is function of a control voltage D(Vcontrol).
Phase Detector (PD): – –
Compares the phase of the signal at the input and output of the VCDL. Depending on the type, produces an error signal that: •
–
Sometimes the control quantity can be a current. In this case we have a Current Controlled Delay Line (CCDL)
–
We will assume that the higher the voltage (or the current) the shorter will be the propagation delay through the delay line.
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•
•
•
It is proportional to the phase difference between the input and output phases; It just gives an indication on the sign of the phase error (bang-bang detector).
Loop filter (LF):
Delay-Locked Loops
– –
Eliminates the high frequency components of the error signal: It can be implemented as: • • •
An RC low-pass filter An active low pass filter A charge-pump and a capacitor 3
DLL Building Blocks •
We will describe details and possible implementations of the DLL building blocks: – Voltage Controlled Delay Line (VCDL) – Phase-Detector (PD) – Loop Filter (LF)
•
All the circuits we will discuss are CMOS circuits.
•
Before proceeding into the circuit details, we need to refresh the basic concepts on the operation of a MOS transistor from the circuit point of view.
•
CMOS: – C: complementary: N and P type transistors – M: Metal gate: Polysilicon in modern technologies… – O: Silicon dioxide dielectric – S: Semiconductor
•
NMOS: – Charge carried by electrons – Turned on by gate voltages positive in relation to the source
•
PMOS: – Charge carried by holes – Turned on by gate voltages negative in relation to the source
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Delay-Locked Loops
4
CMOS Transistors Simple Model •
•
•
In saturation:
•
Circuit:
–
Gate-to-source capacitance
–
–
Voltage controlled current generator between source and drain
Drain of a transistor is loaded by the gate of the next
–
Next gate represents a capacitance to the previous transistor.
Linear region: –
A gate capacitance
–
Voltage controlled resistor between the source and drain
•
Cutoff region: –
Gate capacitance
–
Infinite resistance between source and drain
Drain current used to charge (or discharge) the gate capacitance of the following transistor
I
ds
≅
In saturation D
G
Vds
Vgs S
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G
Vgs Cgs
S
S Delay-Locked Loops
μ ⋅C
(
)
ox ⋅ W ⋅ V − V 2 2 L gs T
Ids
D
I
Vds S 5
The Voltage Controlled Delay Line (VCDL)
Clock in
Voltage Controlled Delay Line
Clock out
1st order
Phase Detector
Error Signal
Delay Control
f
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Delay-Locked Loops
6
Intrinsic Delay in CMOS Circuits Ideal MOS VIN Time it takes to discharge C from Vdd to Vdd/2
Δt =
C Vdd C L ⋅ ≈ ⋅ I 2 μ ⋅ Cox ⋅ Vdd W
VGS
I
(VGS-VT)2 C
VIN Vdd
Assuming AssumingVVTT≈≈00 0 VOUT Vdd 0
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Delay-Locked Loops
t delay
50% level
t 7
CMOS Inverter •
•
Common-source configuration: –
NMOS can only discharge (pull-down);
–
PMOS can only charge (pull-up);
–
Both P and N transistors are thus needed.
CMOS inverter: –
•
in
No static power consumption.
–
PMOS transistors are weaker than NMOS.
–
To compensate:
out CL
Mobility electrons > mobility holes:
Wp/Wn = μn/μp ≈ 3/1 (for Ln = Lp, typically minimum length in digital circuits).
•
Vdd
in
What’s the best way to control the inverter delay: –
Vdd?
–
CL?
–
None of the two!
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out
Delay-Locked Loops
8
The Starved Inverter Vdd
Controlling Iup controls the charging time
Iup
in
out CL
Δtup =
C Vdd ⋅ I up 2
Switching transistor not limiting
Controlling Idown controls the discharging time
Δt down =
C I down
⋅
Vdd 2
Idown in
Delay as short as possible: Iup = Idown = max Switching transistors limiting.
Δt =
out
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Delay-Locked Loops
C Vdd C L ⋅ ≈ ⋅ I 2 μ ⋅ Cox ⋅ Vdd W
9
Biasing the Starved Inverter
Vdd 1:N
Ibias = Iup/N
in
out CL
Vcontrol
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Iup
Idown
Delay-Locked Loops
10
Making Sure it Will Work •
Can we run the starved inverter infinitely slow?.
•
No, must have:
Vdd
t rise = tfall < min(pulse width ) Pulse too short
input output
Filtered out by the starved inverter
in
Iup
out CL
Pulse wide enough
input
1 0
output
1 0
Vcontrol
Pulse appears delayed at the output
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Delay-Locked Loops
Imin
Imin prevents trise and tfall from becoming too long 11
Voltage Controlled Delay Line
Vdd In Inaareal realimplementation implementation these nodes these nodesintroduce introduce poles in the VCDL poles in the VCDLtransfer transfer function. function.Care Caremust mustbe be taken so they are at high taken so they are at high frequencies frequenciesnot notto todisturb disturb the DLL dynamic behavior. the DLL dynamic behavior.
Vcontrol
Iup
in
out
Imin
tdt ==f(V control) )==KK vcdl ××VV control f(V d control vcdlaroundcontrol (linear approximation valid the working point)
(linear approximation valid around the working point)
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Delay-Locked Loops
12
Differential Delay Cell Advantages:
Disadvantages:
•
‘Insensitive’ to common-mode;
•
Consumes static power;
•
Signal and the Inverted signal available.
•
Half of the tail current used to charge/discharge the load;
•
Constant power consumption: low switching noise
•
Differential to single ended converter required to interface with CMOS logic
Vdd 1
1
1
out-
out+
in+
in-
Iup
Vcontrol
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Imin
1
Delay-Locked Loops
2
13
The Phase Detector (PD)
Clock in
Voltage Controlled Delay Line
Clock out
1st order
Phase Detector
Error Signal
Delay Control
f
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Delay-Locked Loops
14
XOR: A Simple Phase Detector Output lags the input by π/2 (T/4)
VCDL input signal VCDL output signal
input
ΦΦerr == err
output error
error
= ½ Vdd
Output lags the input by π/4 (T/8) input output error
= ¼ Vdd
Output lags the input by 3π/4 (3T/8) input
The Thephase-error phase-erroror orphase phase difference differenceisisnot notthe the instantaneous instantaneousvalue valueof ofthe the phase detector output but phase detector output but its itsaverage averagevalue. value. That Thatisisone oneof ofthe thereasons reasons why the loop-filter why the loop-filterisis required. required.
output error
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= ¾ Vdd Delay-Locked Loops
15
XOR Uncertainty VCDL input signal
error
VCDL output signal
Output lags the input by π/4 (T/8)
Output lags the input by 3π/4 (3T/8)
input
input
output
output
error
error
Output leads the input by π/4 (T/8)
Output leads the input by 3π/4 (3T/8)
input
input
output
output
error
error
The phase detector can not distinguish between these two conditions.
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Neither between these two conditions.
Delay-Locked Loops
16
Non-Linear and Limited Range [Volts] K pd
K pd =
Vdd
dV = 0 dφ
[rad]
π
0 0 Output phase Leads
¾π
2π
π/2 Output phase Lags
•
Slope: Kpd, [V/rad] or [V/s];
•
Slope sign depends on the operation region: –
Negative gain → Positive feedback;
–
Positive gain → Negative feedback;
•
Gain inversion occurs at integer multiples of π;
•
XOR phase detector must work with a static phase difference of π/2; –
•
For the XOR, a phase difference equal to π/2 is ‘zero error phase’;
The type of phase detector dictates the static phase difference.
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Delay-Locked Loops
17
XOR Non-Idealities •
•
XOR ripple is at twice the operation frequency: –
Advantage for RC filtering;
–
A problems if a charge-pump filter is used.
in out error
XOR drawback: sensitive duty-cycle;
Different duty-cycles
Same phase difference
in out error
Different averages
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Delay-Locked Loops
18
More Non-Idealities in
in
out
out
error
error
Gain saturation (for 25% duty-cycle)
in out
0
error
•
π
Duty-cycle distortion also causes ‘saturation’ of the phase detector transfer function
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Delay-Locked Loops
19
The DFF Phase Detector VCDL input signal
D
Q
error
•
Sign information only:
VCDL output signal
Output lags the input
•
–
No phase error magnitude information;
–
It distinguishes early or late only;
–
It is called a bang-bang phase detector.
Loop operation: –
input •
When in lock the phase change occurs virtually every clock cycle and the average phase error becomes zero.
Its advantages are:
output
–
simplicity of operation;
–
error
Operation possible at the maximum FF operation frequency;
–
Minimum pulse width 1/f;
–
The phase range spans from –π to +π.
–
Insensitive to duty-cycle distortion in the CK input (however: duty-cycle distortion on the D input creates asymmetry in the transfer function)
Output leads the input input
vdd
output −π
error
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π
0 Delay-Locked Loops
20
DFF PD Implementation
SR2
•
Carefully design one.
•
To avoid phase errors and Metastability:
Dummy gate
–
Internal nodes → same fanout;
–
Gates → the same driving capability;
–
Every two gates in the same latch → same fan-in;
–
The latch SR1 is critical → should reach its final state as fast as possible;
–
Decision in a fraction of the reference clock period → Otherwise increased jitter.
SR3 •
D SR1 Dummy gate
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Delay-Locked Loops
Layout is critical for operation: –
Device matching;
–
Large area devices;
–
Layout as symmetrical as possible;
–
Keeping the wire loading identical on corresponding nodes.
21
The Loop Filter (LF)
Clock in
Voltage Controlled Delay Line
Clock out
1st order
Phase Detector
Error Signal
Delay Control
f
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Delay-Locked Loops
22
A simple loop filter: RC Low-pass
VCDL input signal
VCDL control voltage
VCDL output signal
VVcontrol ==KKpd ×× control pd
•
KKpd ==VVdd//ππ [V/rad] [V/rad] pd dd
The simplest possible filter is an RC low-pass filter;
•
•
Output voltage controls the VCDL.
•
•
Filter bandwidth: a few or several decades lower than fref;
•
In steady state conditions, the filter DC output voltage is proportional to the phase error.
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Advantage: –
Disadvantage: –
•
Simplicity Corrective action can only be achieved at the price of a phase offset.
The phase offset value depends on the phase detector gain:
Delay-Locked Loops
–
Small gain Kd → large phase offset!
–
Phase detector gain is dictated by Vdd 23
Finite DC Gain is a Disadvantage
T1
π/2
T2
> π/2
T2 < T 1
= ½ Vdd •
VCDL for a reference signal with period T1. –
•
> ½ Vdd
propagation delay T1/4 achieved exactly at Vdd/2;
Reference period changed to T2 < T1 –
To run with a shorter propagation delay a higher VCDL control voltage is necessary;
–
With the RC filter, higher voltage can only be obtained at a cost of an extra phase lag;
–
This is undesirable → it introduces an error in the VCDL propagation delay.
–
The error can be reduced by increasing the open-loop gain: K = Kpd Klf Kvcdl. (Klf is the filter gain, 1 for the passive RC filter).
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Delay-Locked Loops
24
Improving the RC Filter • •
Increasing the open-loop gain reduces the phase offset:
•
Draw backs: Small Vcnt fluctuations converted in large variations of the VCDL propagation delay (jitter);
–
Secondary poles might result in a badly behaved transient response or even instability.
Increasing Vdd increases Kpd (Kpd = Vdd/π):
•
–
–
Not a practical solution;
–
The gain increase would be small.
More effective:
•
– Add a gain stage between the filter and the VCDL:
The XOR phase detector and the passive RC filter are thus not the favorite choice for integrated DLLs
– Increase the gain of the VCDL (Kvcdl)
VCDL
in out
out
G
To Toreduce reducethe thephase phaseoffset, offset, add gain or increase K add gain or increase Kvcdl vcdl
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Delay-Locked Loops
25
Capacitor: A Current Integrator •
Consider what happens when a current is fed to a capacitor:
•
The voltage across the capacitor (V) is simply the time integral of the current (I) being fed to the capacitor: t
1 V (t ) = ∫ I (t ) dt + V0 C0 •
I (t ) ∝ Φ err (t )
We can thus easily integrate the phase error if we feed to a capacitor a current that is proportional to the phase error ‘measured’ by the phase detector: t
I
V t
1 ( ) Φ t dt ∝ I (t ) dt ∫ err ∫ C0 0
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Delay-Locked Loops
26
Active Loop-filter: Charge-Pump + Capacitor Icp VCDL in
D
Q
VCDL out
Vcontrol
late
Vcontrol early
Vcap
error
Icp
Late = lag → sign(Φerr) = 1 Early = lead → sign(Φerr) = -1
Vcontrol (t ) = Vcap (t ) =
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I cp C
t
∫ sign(Φ err (t )) dt + V0 0
Delay-Locked Loops
27
Charge-Pump for Bang-Bang Detector •
M1: current sink, M2: current source;
•
M3 and M4: switches:
•
•
•
Alternatively closed and opened:
–
Current always flows into or out of the filter capacitor (never directly between Vdd and ground);
M2
Reference leads: –
M4 closed, M3 opened
–
Control voltage increases.
M4
–
M3 closed, M4 opened
–
Control voltage decreases
Vcontrol
error
VCO leads:
M3
Keep sink and source currents well matched: –
•
Vdd
–
Icp
minimize static phase error;
Charge sharing effects need be controlled (discussed later).
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C
Delay-Locked Loops
M1
28
The Delay-Locked Loop
Clock in
Voltage Controlled Delay Line
Clock out
1st order
Phase Detector
Error Signal
Delay Control
f
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Delay-Locked Loops
29
Bang - Bang Operation Overview
in
out
D
Q
Q
Late Vcontrol
Early
in out Early
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Late
Late
Late
Delay-Locked Loops
Early
Late
30
Bang-Bang Operation Tradeoffs Tracking jitter:
Tradeoffs:
•
•
The loop tracking behavior introduces jitter: –
–
In lock output phase constantly oscillates back and forward around the phase of the reference signal: It is a result of no phase error magnitude information.
•
Possible to reduce the loop tracking jitter to insignificant levels;
•
Other jitter sources: –
Thermal and shot noise;
–
Substrate noise;
–
Power supply noise.
•
•
•
Optimization for low-jitter: –
Increase the loop-capacitor C;
–
Decrease: Icp and Kvcdl.
Optimization for fast-lock: –
Decrease the loop-capacitor C;
–
Increase: Icp and Kvcdl.
Optimization for low-jitter and fastlock: –
It is possible to optimize for both:
–
Use a large Icp during lock-acquisition;
–
Use a small Icp after locking.
Optimization against substrate and power supply noise: –
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Delay-Locked Loops
Same as for fast-lock;
31
DLL: linear analysis •
Loop filter: –
•
Continuous time approximation:
Charge-pump + capacitor.
–
Phase detector: –
•
•
Considered Linear → signal proportional to the phase error.
•
Phase detector output: –
Pulse of duration proportional to the phase error (e.g. ΔT(high)-ΔT(low) in an XOR phase detector).
A single pole is present in the loop filter: –
•
Valid for bandwidths a decade or more below the operating frequency. (Keep in mind that DLLs are in fact nonlinear devices.)
The DLL is a 1st order network.
Combination charge-pump and loopcapacitor: –
Acts as a perfect integrator;
–
Modeled as an integrator.
VCDL
PD
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∫ dt
Delay-Locked Loops
32
DLL Modeling Choice of variables: •
•
DLL response formulated in terms: –
Input delay;
–
Output delay; The VCDL delay: DO(t) or DO(s)
Phase detector output is active during this fraction of the reference period
Input delay: –
•
PD
Output delay: –
•
DO (s)
Δt DI ( s) − DO ( s ) = T T
The delay to which the phase detector compares the output delay: DI(t) or DI(s)
Note that DI(t): –
It is phase detector dependent;
–
It s frequency dependent;
Δt T
∫ dt
Vcont
Δt I cp = ⋅ T s ⋅C
DO ( s ) = K vcdl ⋅ Vcont ( s ) VCDL
Vcont (s )
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Delay-Locked Loops
33
DLL Transfer Function DO(s)
1 s
PD
Phase error
DO (s) =
[D I ( s ) −
D O (s)]
T
⋅
I cp s ⋅C
⋅K
vcdl
Charge pump Duty-cycle Control voltage VCDL propagation delay
DO (s) 1 H (s) = = s D I (s) 1+
ωn
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• •The loop Theclosed closed looptransfer transfer st function is 1 order st function is 1 order • •ItItisischaracterized characterizedby bythe the natural frequency ω natural frequency ωn
ωn =
I cp ⋅ K
vcdl
T ⋅C
n
Delay-Locked Loops
34
The DLL is a 1st Order System
ωn =
I cp ⋅ K vcdl
Dfinal
T ⋅C D final d D (t ) = dt t =0 τ
ωn naturally ‘tracks’ the reference frequency.
•
τ=
Designing a DLL it is equivalent to choose its natural frequency ωn: –
Choose Icp and C.
–
Kvcdl ‘fixed’ by the VCDL design and technology parameters (some degree of control but not much).
–
T is fixed by the operation frequency/frequencies.
–
Since the system is 1st order it is inherently stable: •
ωn
•
•
Make sure the higher order (unwanted but unavoidable poles) are at least 10 times higher that ωn.
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t
1
Delay-Locked Loops
The closed-loop behavior is similar to that of a 1st order low-pass RC filter: –
Settling to 2% → t ≈ 4τ
–
Settling to 0.1% → t ≈ 7τ
Fast settling requires large ωn: –
Trades off against low tracking jitter.
–
ωn might start approaching the higher order poles.
35
DLL Design •
ωn = •
I cp ⋅ K vcdl T ⋅C
The parameters: –
Icp
–
C
–
Kvcdl
Self-biasing techniques can make ωn track the operation frequency over several decades: see Maneatis 1996
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F = 100 MHz T = 10 ns
–
Icp = 1 μA
–
C = 100 pF
–
Kvcdl = 2 ns/V
–
ωn = 2 krad/s
–
τ = 0.5 ms
Notice that:
ωn would track the operation frequency (i.e. proportional to 1/T) if the other parameters were ‘absolutely’ constant: –
–
This leads to:
are technology, temperature and supply voltage dependent •
Example:
•
The DLL bandwidth is many orders of magnitude lower than the operation frequency.
•
When locked to a low jitter clock signal this PLL will display low tracking jitter.
•
A VCDL, when subjected to substrate or power supply noise, will generate jitter. Under such circumstances, a DLL with such a low bandwidth will be ineffective tracking the input phase and thus suppressing its own jitter.
Delay-Locked Loops
36
Bang-Bang DLL Nonlinear Analysis ¾
¾
When a DLL uses a DFF as the phase detector, the continuous time approximation can not be used.
Period
Reference
Tfinal
Simple expressions can be found for: –
The response to a period step;
–
The tracking jitter.
VCDL
Tinitial
t
Phase step: The new period is 2/3×Ti < Tf < 2×Ti:
•
–
DLL will regain lock to the new phase;
–
The VCDL delay will ramp to the new value.
The DLL will try to catch the new period at a rate given by:
The new period is outside the above bounds: –
I cp dVcontrol d D(t ) = K vcdl = K vcdl dt dt C
The Phase-Detector will give the wrong phase information and the DLL will lose phase lock.
Units: [rad/s] or [s/s]
Example: Using the previous example the tracking slope is: 20 ns/ms
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Delay-Locked Loops
37
Frequency Step f2 > f1 T1
The DLL is locked to the reference signal (period T1)
in out
T2 < T 1
Phase is detected late, the VCDL delay is going to be decreased.
in out
Immediately after the frequency step (period T2 < T1) the VCDL delay is too big and the PD will activate the late signal until the de VCDL propagation delay becomes equal to T2 VCDL input period
in
VCDL D
Q
Q
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VCDL propagation delay
out
Late
Early
C.P.
Delay-Locked Loops
38
Frequency Step f1 > f2 T1
The DLL is locked to the reference signal (period T1)
in out
Immediately after the frequency step (period T1 < T2) the VCDL delay is too short and the PD will activate the early signal until the de VCDL propagation delay becomes equal to T2
T2 > T 1 in
VCDL input period
out Phase is detected early, the VCDL delay is going to be increased.
in
VCDL D
Q
Q
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VCDL propagation delay
out
Late
Early
C.P.
Delay-Locked Loops
39
Frequency Step: Limit Values T1
T1
in
in
out
out
T2
T2
in
in
out
out
If T2 < 2/3 T1 the phase detector will activate the early output instead of the late. The delay will increase instead of decreasing.
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Delay-Locked Loops
If T2 > 2 T1 the phase detector will activate the late output instead of the early. The delay will decrease instead of increasing.
40
Bang-Bang Tracking Jitter Jitter: • Uncertainty on the position of the falling and rising edges. • Seen in a scope as ‘thick’ traces on the rising and falling positions.
T in
late
Jitter
out
early •
Ideally every clock cycle the phasedetector should alternate between an early and a late decision.
•
In practice, due to charge-pump unbalance or jitter, it is very likely that the PD decision will be frequently maintained during two consecutive clock cycles to either side.
•
The minimum P-P tracking jitter is thus given by:
I cp d D(t ) 4⋅ ⋅ T = 4 ⋅ K vcdl ⋅T dt C
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ΔVcont = 4 ⋅
I cp C
⋅T
ΔVcont
Example: Using the tracking slope from the previous example: Jpp = 4 × (20 ns/ms) × (10 ns) Jpp = 0.8 ps The tracking jitter can be thus made to be very small. The jitter is likely to be dominated by thermal, supply and substrate noise.
Delay-Locked Loops
41
DLL Lock Acquisition Typical Bang-Bang DLL startup procedure: 1. Set the VCDL to its minimum value (maximum control voltage) 2. Force the VCDL delay to increase until the phase detector gives a consistent early indication (e.g. 32 consecutive early detections) 3. Once the PD consistently indicates early, pass the control of the loop to the phase detector which will finally take the DLL to lock.
1st phase
VCDL set to its minimum delay
in out Here the PD wrongly indicates late
2nd phase in out Here, due to jitter, the PD sometimes gives the correct and sometimes the wrong indication
3rd phase in out The PD is now in a ‘safe’ zone, it correctly and consistently indicates early.
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Delay-Locked Loops
42
Charge Sharing •
Charge-pumps perform almost like ideal integrators however charge sharing might degrade their performance. This node charges to Vdd when M4 is open
Vdd
When M4 closes Vcontrol jumps of:
ΔVcont =
M2 Cd2
When M3 closes Vcontrol jumps of:
ΔVcont = −
M4 Vcontrol
late M3
C Icp
Cd1
M1
Cd 2 ⋅ (Vdd − Vcont ) C + Cd 2 Cd 1 ⋅ Vcont C + Cd 1
Notice that: • The voltage jump is proportional to the control voltage itself; • ≈ proportional to Cd1 and Cd2; • ≈ inverse proportional to C; (usually C>> Cd1 or Cd2): Example: If C = 100 pF, Cd1 = 10 fF and Vcontrol = 1V: ΔVcontrol = -100 μV Compare with: Icp×T/C = 100 μV
This node discharges to gnd when M3 is open
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Delay-Locked Loops
43
Charge Sharing Control Vdd Icp
M2
•
Charge sharing is eliminated.
•
Clock feed-through is present through Cgd of M5 and M6. However the voltage swing at the gate of these transistors is relatively small
M4 M6 late
Vcontrol Voltage Voltageon onthis thisnode nodenever neverrises rises much above V -V . So turn-on th much above Vdd dd-Vth. So turn-on isisrelatively fast. relatively fast.
M5 M3 C
Icp
Voltage Voltageon onthis thisnode nodenever neverdrops drops much below V . So turn-on much below Vthth. So turn-onisis relatively relativelyfast. fast.
M1 RC time constant
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Delay-Locked Loops
44
Delay chain feed through
Parasitic Cdg introduces ripple on the control lines.
In lock the raising and falling edges effects cancel each other.
Vdd To maintain symmetry, buffer the dummy cell control lines.
Iup
Vcontrol
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in
out
Imin
Delay-Locked Loops
45