Outline •

Introduction

•

Delay-Locked Loops

•

DLL Applications

•

Phase-Locked Loops – PLL overview – Building blocks: • VCO • PD • LF

– PLL analysis: • Linear • Nonlinear

– Simulation: • PFD PLL with Verilog • Bang-Bang PLL with MATLAB

•

PLL Applications

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Phase-Locked Loops

1

Why Phase-Locked Loops? Clock skew control and frequency multiplication Clock skew control and frequency multiplication

IC The PLL automatically nulls the phase and frequency difference between these two points

Ext. CLK

Clock pad

Int. CLK

4

Internal clock

Q

Output pad

PLL clock route Clock buffers and interconnects introduce delay

Frequency here 4 times the external clock frequency

External clock

Internal clock

Phase aligned

Output data

Output data registers delay [email protected]

Phase-Locked Loops

2

The Essence of a PLL Unlocked: Uncoordinated hands, gets nowhere

Locked: Finally learned, goes where he/she wants

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Phase-Locked Loops

3

PLL Block Diagram 1st order

Reference

Phase Detector

LF

Error Signal

Frequency Control

VCO

Out

f

Phase-Locked Loop functional blocks •

•

Phase Detector (PD): –

Voltage Controlled Oscillator (VCO): –

–

–

As the name indicates is an oscillator whose frequency is controlled by a voltage: fout = F(Vcontrol)

–

•

Sometimes the control quantity can be a current. In this case we have a Current Controlled Oscillator (CCO) We will assume that the higher the voltage (or the current) the higher the frequency

Compares the phase of the reference signal to the VCO phase Depending on the type, produces an error signal: •

–

•

Phase detectors can be also frequency sensitive; in this case they are called Phase-Frequency Detectors (PFD).

Loop filter (LF): – – –

Eliminates the high frequency components of the error signal Introduces a loop-stabilizing zero It can be implemented as: • • •

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Proportional to the phase difference between the input and output phases; Gives just an indication on the sign of the phase error (bang-bang detector).

Phase-Locked Loops

An RC low-pass filter An active low-pass filter A charge-pump a resistor and a capacitor 4

PLL Basic Operation

err(t) in(t)- out(t) in(t)

Reference

err(t)>

out(t)

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

5

The VCO

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

6

Starved Inverter VCO The VCO is an oscillator • The oscillation frequency depends on the control voltage • It is usually modeled as: t

f (t )  K vco  Vcnt (t )  f 0

 (t )   f (t ) dt   0 0

1  ( s )  K vco   Vcnt ( s ) s

Vdd

Practical advice: • An odd-number of inverters is mandatory; • Always buffer the output signal; • Ensure a minimum oscillation frequency; • Preferably use a minimum of 3 inverters. The TheVCO VCObehaves behavesas as a phase integrator a phase integrator

Ibias out

Vcontrol

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Imin

Phase-Locked Loops

7

Differential VCO cell Bias P

To other cells

Vdd

C gs , P

×2

×1

out-

I

×1

×1

×1 g m, p

out+



in+

Cgs, N  C gs, P 

in-

g m, p

C gs , N

2×I

Vcontrol

To other cells

×1

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×2

Phase-Locked Loops

8

VCO Transfer function VCO - Run: 18/09/2000 (Extraction model: close interconnect), Fit order = 3 3.5  =-1.5, T=125C, Vdd=2.25V

3

 =0, T=25C, Vdd=2.5V  =+1.5, T=-55 C, Vdd=2.75V

Frequency (GHz)

2.5

2

Target operation frequency: 800 MHz Kvco = -2.36 GHz/V

1.5

Kvco = -3.72 GHz/V

1

0.5

Kvco = -1.17 GHz/V 0 -1500

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-1400

-1300

-1200

-1100 -1000 Control voltage (mv)

Phase-Locked Loops

-900

-800

-700

-600

9

LC VCO Vdd Voltage controlled capacitance Implemented with PMOS transistors Out-

f0 

1 2  L  Ceq

Out+ Frequency selective load

Vcontrol

L

Equivalent model

Ceq

-1/Gm

-Gm R Resistive losses

[F]

Compensates losses

PMOS Capacitor

7.00E-10

Q

L / Ceq R

6.00E-10 5.00E-10 4.00E-10

Ignore absolute value of the capacitance. Measurements made on a VERY BIG transistor to minimize experimental errors. [email protected]

3.00E-10 2.00E-10 1.00E-10

Measurement Simulation

0.00E+00 -2.5

-2

-1.5

-1

-0.5

0

0.5

Phase-Locked Loops

1

1.5

2

2.5

Vgs 10

The Phase Detector

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

11

The Analog Multiplier as a Phase Detector A  cos(  t ) A  cos(  t )  B  cos(  t   )

Same frequency

B  cos(  t   )



Phase difference

A B cos( )  cos(2    t   ) 2

DC term

Double-frequency term Function of the signals amplitudes!

Low pass filtering

 Vout  

A B cos( ) 2

100

Function of the phase difference

(A  B)/2 [%]

50

0

K PD 

Maximum Maximumfor for==/2 /2

-50

-100 -2



d A B  Vout    sin( ) dt 2

-1 

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0  [rad]

1

2 Phase-Locked Loops

12

Gilbert Cell as an Analog Multiplier

Id2

Id1

I d  I d1  I d 2  Valid for:

W2/L2

  Cox 2

2   Cox Vvco

2



I ss

 2

W1 W2   Vref  Vvco L1 L2

 1

Vvco W1/L1

Vref

Iss

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Phase-Locked Loops

13

Phase Frequency Detector VCO lags VCO lags ref 1

D

Q

late vco

ref RST

1

D

Q

late

early

vco RST

early 1 error 0

VCO VCOleads leads ref vco late

Phase error = late - early Pulse width: proportional to phase error Sign: > 0  VCO lags < 0  VCO leads

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early 0 error -1 Phase-Locked Loops

14

PFD: Frequency sensitivity VCO slow VCO slow ref vco late early 1 error 0 -1 VCO fast VCO fast ref vco late early 1 error 0 -1 [email protected]

Phase-Locked Loops

15

PFD Characteristics

Verr Vdd -4

-2 2

4



-Vdd

vco

vco

Late = 0 Early = 1

ref

Late = 0 Early = 0

ref

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Late = 1 Early = 0

ref

vco

Phase-Locked Loops

16

The Loop Filter

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

17

Charge-Pump and RC Loop Filter

Loop Filter HLF(s)

LF transfer function:

reference

H (s)  R1

Vcontrol

Pole:

vco R2

1  s  R2  C 1  s  ( R1  R2 )  C

fp 

1 2  ( R1  R2 )  C

fz 

1 2  R2  C

Zero:

C

The pole and the zero are coupled

Finite FiniteDC DCgain gain(=1) (=1)Frequency Frequencyand andphase phaselock lockcan canonly onlybe beachieved achievedatataacost costofofaaphase phaseoffset! offset!

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Phase-Locked Loops

18

Active Filter: Charge-Pump + RC network err ,n (t ) 

err  late(t )  early (t ) 2

err , n (t )   1,1 late

ref PFD vco

Vcontrol (t )  Vres (t )  Vcap (t )

early

Charge Pump

Vcontrol

t   1 Vcontrol (t )  I cp   R  err ,n (t )   err ,n (t ) dt   V0 C0  

R

Integral term controlled by ‘C’ Proportional term controlled by ‘R’

C

Current magnitude Icp affects both

Zero at:

Infinite gain at DC

H LF ( s )  I cp 

1 s  R C s C

fz 

1 2  R  C

Independent

Pole at the origin [email protected]

Phase-Locked Loops

19

Charge Pump Implementation Vdd M2

late

late

M6

M4

late

late Vcontrol

early early

M5

M3

early M1

Icp

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Phase-Locked Loops

early R C

20

Charge Pump Operation ref

vco

t1 late

t2 early

Vcontrol

VI 

I cp

 t1 C VP  R  I cp

VP   R  I cp

VI  

I cp C

 t 2

t [email protected]

Phase-Locked Loops

21

The PLL

Reference

1st order

Phase Detector

Error Signal

LF

Frequency Control

VCO

Out

f

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Phase-Locked Loops

22

Charge-Pump PLL with PFD Assume the PLL is locked in = out:

Phase error

‘ON’ time for either ‘Late’ or ‘Early’

ton 

err in

Q  I cp

err ( s )  in ( s )  out ( s )

Lumped contributions of: • Phase-Frequency Detector • Charge-Pump • Filter impedance

Average current in one cycle

err in

id  I cp

err 2

Vcnt ( s )  I cp 

err ( s )  Z ( s) 2

The charge delivered in one cycle is proportional to the phase error err

late

in PFD

out ( s ) 

out , out

early

Charge Pump

±Icp

Vcnt

C

Z

K vco  Vcnt ( s ) s

[3]

[1] [2] [3]

VCO

R

[2]

Kvco in rad/(s.V)

VCO phase

in , in

[1]

K vco  I cp  Z ( s ) out ( s)  H ( s)  in ( s) 2  s  K vco  I cp  Z ( s )

[4]

err = in - out

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Phase-Locked Loops

23

A Second Order System Z (s)  R 

1 s C

[4] [5]

[5]

H ( s) 

I cp  (1  R  C  s )  K vco 2  C  s 2  I cp  (1  R  C  s )  K vco

[6] can be put in the form:

A zero appears in the transfer function: It is used to compensate the PLL response

H (s) 

(1   z  s ) 1 2 2  s   s 1 2

Compensating zero time constant

 z  R C n 

I cp  K vco

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Natural frequency

2  C

R C  n 2

K  2    n 

[7]

n

n

The loop is second order



[6]

Damping factor

R  I cp  K vco 2

Any two of these parameters define the linearized, time-averaged behavior of the PLL

Loop gain

Phase-Locked Loops

24

PLL Stability Open-loop transfer function:

H O (s) 

I cp 1  s  z K vco   s C s 2

log |HO(s)|

H O (s) 

I cp K vco  2 s 2  C

H O ( s)  For acceptable phase margin Place the zero 1/z well below n n cross over frequency of HO(s) if no zero was present)

0

1

z

n

Increasing K

(Slope = -2)

I cp  z K vco   2 C s

(Slope = -1)

log 

C

Im Two poles Re

K  2    n 

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Phase-Locked Loops

R  I cp  K vco 2

25

Jitter Peaking

log |H(s)|

Low damping ratio High damping ratio

H ( s) 

(1   z  s ) 1 2 2  s   s 1 2

n

0

n

log 

1

z

Over a given band of frequencies, H(s) will exceed unity. Jitter frequencies within this band will be amplified

For large damping ratios the zero frequency is below the closed-loop poles

To Tominimize minimizejitter jitterpeaking peakingkeep keepthe thefirst firstclosed-loop closed-loop pole next to the zero by using high loop gains pole next to the zero by using high loop gains

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Phase-Locked Loops

26

Charge-Pump PLL with DFF Phase Detector Bang-bang (proportional) branch

fdiv, div ÷M

fdiv, div D

Q

early / late

Kbb

Vpd

ref

VCO Charge Vcnt Pump

Kvco

Phase detector: only early/late information

Integral branch

 ( )dt div ref early late

The VCO frequency is a function of the integral and proportional control paths:

1 f (t )  K bb  V pd (t )  K vco  Vcnt (t )  f 0 2

1  f (t )  K vco      V pd (t )  Vcnt (t )   f 0 2 

 [email protected]

Phase-Locked Loops

K bb K vco 27

Steady State Operation Phase tracking

fdiv

÷M

D

Q

Kbb

Vpd

early / late

ref

VCO

fref

Charge Vcnt Pump

The loops are non-interacting: • Bang-bang branch • Integral branch

 phase tracking loop (binary control)

Frequency tracking

 frequency tracking

In steady state conditions:

f [Hz]

• VCO frequency switched between two discrete frequencies (proportional branch) • Phase ramps up and down tracking the incoming phase (proportional branch)

fdiv

fref

• The integrator follows the ‘DC’ component of the phase detector, tracking the average frequency. [email protected]

Kvco

Phase-Locked Loops

t

28

Proportional Branch fdiv

f [Hz]

Tracking TrackingJitter Jitter Ref

2  Fstep

fref

VCO

Divider t t’

t Assuming lock Negligible fint over a cycle

1 Fstep    K bb  V 2

Peak-to-Peak phase detector voltage

Jbb=t’-t Assuming that: • Most decisions alternate state • Occasionally two consecutive decisions with no state change occur

J bb  

Fstep

1      K vco  V 2

J bb  

Kvco and Kbb in Hz/V

2  M  Fstep f vco

[1]

2

M    K vco  V f vco

2

[2]

f vco  M  f ref (in lock) 2

Design equation [email protected]

Phase-Locked Loops

Fstep

f  vco  J bb 2M

[3] 29

Integral Branch For Forthe thePLL PLLto tobe bestable stablethe theintegral integraland andthe the bang-band loops must be non-interacting bang-band loops must be non-interacting

‘Integral ‘IntegralBranch BranchJitter’ Jitter’

Phase increment during t = Tref

Ref

 (t )  bb (t )  int (t )

VCO

Integral contribution Divider

Bang-bang contribution Jint

For the loops to be non-interacting:

Vcnt

bb (t )  int (t ) The integral control voltage ramps up or down in between two phase detector decisions

J int 

I cp C

 K vco 

Stability Stabilitycriteria criteria

M3 f vco



3

C  V bb 1 K bb    f vco   1 I cp int M K vco

J int  J bb Necessarily [email protected]

Phase-Locked Loops

30

PLL Simulation

err

t

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Phase-Locked Loops

31

PLL Modeling with Verilog Verilog  Hardware description language for digital circuits Used for: • Hardware description • Hardware simulation • Source code for logic compilers reference

r v

u d

(digital)

Charge-Pump and Loop-Filter

VCO delay controlled by a 32 bit number to match the analogue precision

32

(analogue + digital)

VCO (digital)

÷M (digital)

Analogue is modeled inside with real variables

Algorithm: • Slice the time in very thin intervals (much smaller than Tvco) • Make the time advance in these time increments • At every time increment do: • Update the phase detector outputs • Calculate the new filter voltage according to the phase detector state • Update the VCO frequency as function of the filter voltage [email protected]

Phase-Locked Loops

32

Phase Detector and VCO Phase Frequency Detector `timescale 1 fs / 1 fs module ThreeStatePD (down, up, r, v); output

input

down, up;

// Early signal // Late signal

r, v;

// Reference input // VCO input

wire

r, v, reset;

reg

up, down;

initial

begin up = 0; down = 0; end

always @ (posedge r) up