Outline - Paulo Moreira

D. A. Johns and K. Martin, “Analog Integrated Circuit Design,” John Wiley & Sons 1997, ISBN 0- ... B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal on Solid-State ... http://www.ife.ee.ethz.ch/~ichsc/ichsc_chapter11.pdf.
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Outline •

Introduction



Delay-Locked Loops



DLL Applications



Phase-Locked Loops



PLL Applications – Frequency Synthesizers – Serializer – Clock Recovery – Jitter Filtering Application

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PLL Applications

1

Frequency Multiplier H ( s) =

fref = M×fref fref

PLL

fout

f=fref

÷M

log |H(s)|

(1 + τ z ⋅ s ) 1 2 2 ⋅ξ 1 s s ⋅ + ⋅ + M ⋅ ωn M ωn2

When M is large: • Use large damping ratios to reduce jitter peaking • Use a low phase noise reference if possible. • PLL bandwidth: • Reduce for a noisy reference and low noise VCO • Increase for low noise reference and noisy VCO

Above the 2nd pole the reference jitter is filtered

Jitter spectral components in this band are amplified! |H(0)| = M

log M

0

1

p1

p2

log ω

τz [email protected]

PLL Applications

2

Frequency Synthesizers fref

÷N

PLL

fref

fout

÷M

f=fref/N

f out =

÷N

f=fref/N

M ⋅ f ref N f out

M = ⋅ f ref N ⋅P

PLL

÷M

÷P

fout

• PLL input frequency is fref/N

• PLL input frequency is fref/N

→ PLL bandwidth less than fref/(10×N) for stability.

→ PLL bandwidth less than fref/(10×N) for stability.

→ Long settling time.

→ Long settling time.

→ Frequency spacing fref/N.

→ Frequency spacing fref/(N×P).

For the same fout, the architecture on the right has a P times higher input frequency: → Higher loop bandwidth (+) → Lower settling time (+) → Higher VCO frequency (-)

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PLL Applications

3

Serializer Parallel Data

Clock

8

Register

PLL

8

8B/10B Encoder

÷10

10 fclock

Register 10

10×fclock

Shift Register 1 Serial Data • Use a low noise clock source. • Use a wide-band PLL [email protected]

PLL Applications

4

Clock Recovery A PLL can’t lock to NRZ data

But it can lock to such a signal No spectral-line at the bit rate frequency

NRZ Data d

Spectral-line at the bit rate frequency present

Edge detector

NRZ data

τ

D

PLL

Q

Retimed data

Ideal sampling instant

d

Problem: Difficult to match the delay of the two paths so that the recovered clock samples the data at the middle of the data eye over all process, temperature and supply variations.

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PLL Applications

5

Hogge Phase Detector Phase detector output

Variable pulse width: depends on the phase error

Locked Reference pulse: width = T/2

NRZ

φerr = 0

clk p1

p2 p1 p2

NRZ data

D

Q

D

Q

Vint Clock Lags NRZ

VCO clock

φerr Retimed data

−2π

−π

p1

π





p2

φ

(assuming maximum data transition density) [email protected]

clk

PLL Applications

Vint

∆Vcnt 6

Modified Triwave Phase Detector p1

NRZ data

D

p3

p2

Q

D

Q

D

p4

Q

D

Q

VCO clock Retimed data

Hogge PD

Modified Triwave Detector

NRZ

NRZ

CLK

CLK

Vint

Vint

Positive net area

Average value depends on the transition density

→ Data dependent jitter!

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Zero net area

PLL Applications

triwave

Average value ‘independent’ of the transition density

→ ‘No’ data dependent jitter!

7

Alexander Phase Detector - Principle •

It is a bang-bang detector: –



Clock is early

Only early/late information

To take the Early/Late decision: –

1st Look for transitions



2nd Take an Early/Late decision at every transition

S1



Three samples of the serial data are necessary to find the transition and resolve the phase relation ship.



No data transition present:









S1 = S2 = S3



S1 ⊕ S3 = 0 and S1 ⊕ S2 = 0



Charge-pump: Hold

Data transition + Early clock:

S2

S3

Clock is Late



Sample S1 ≠ S3 and S1 = S2



S1 ⊕ S3 = 1 and S1 ⊕ S2 = 0



Charge-pump: Down = (S1 ⊕ S3) & ~(S1 ⊕ S2)

S1

S2

S3

Data transition + Late clock: –

Sample S1 ≠ S3 and S1 ≠ S2



S1 ⊕ S3 = 1 and S1 ⊕ S2 = 1



Charge-pump: Up= (S1 ⊕ S3) & (S1 ⊕ S2)

The falling edge of the clock aligns with the data transition instants: –

In lock, S1 or S3 are thus at the optimum sampling instants

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PLL Applications

8

Alexander Phase Detector – Implementation I

×2 load Sampling FFs

NRZ data

D

Q

S3

D

FF3

VCO clock

×3 load

Delay FFs

Q

S1

X

FF1

Retimed data FF4

D

Q

FF2

S4

D

Q

S2

Y

×1 load

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Down =

X & ~Y

Up

X &

=

PLL Applications

Y

“asymmetric equations !

9

Alexander Phase Detector – Implementation II •



Performs the same function but: –

All nodes are equally loaded;



Symmetrical logic equations;

These are important to maintain low static phase offsets in high speed circuits ×2 load Sampling FFs

NRZ data

D

Q

S3

D

FF3

VCO clock

×2 load

Delay FFs

Q

S1

Y

FF1

Retimed data FF4

D

Q

FF2

S4

D

Q

S2

X

×2 load Down = ~X & Up

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=

Y

X & ~Y

PLL Applications

“symmetric equations !

10

Jitter Filtering Application

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PLL Applications

11

Band-pass Filter •

Designed as a high Q filter precisely tuned to the input signal frequency

Disadvantages: •

Designed for a single frequency



Filter bandwidth: smaller or much smaller that the signal side-bands



Phase is strongly dependent on “tuning”



Surface Acoustic Wave (SAW)



An auxiliary phase alignment mechanism is required



Zero-crossing + limiting amplifier required to avoid: FM → AM → Phase-Noise



Center frequency depends on temperature



Strict manufacturing tolerances required



Hi-Q filters difficult to integrate

Advantage: •

Passive implementation

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PLL Applications

12

PLL as a Jitter Filter •

For a PLL to act as a jitter filter the VCO needs to be quieter than the reference signal.

Advantages: •

Self tuning to the carrier frequency



Can operate with a relatively large range of carrier frequencies



Loop-band width can be made very small



Easily integrated



Tight manufacturing tolerances not required

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Disadvantages: •

VCOs are noisy



Very low noise VCOs require:

PLL Applications



Hi-Q inductors (difficult to integrate)



Voltage Controlled Crystal Oscillators (VCXO)

13

VXCO based PLL •

Characteristics:



– fin = 40 MHz

– Two control branches: • Bang-bang: phase and frequency control

– BW = 7 kHz – M=4



• Integral: average frequency control

Phase detector: – Bang-bang type

– Almost independent optimization of Kbb and Kint

– Only early/late decision



Control loop:

VCXO – Two control ports • Bang-bang control • Continuous control

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PLL Applications

14

VCXO •

VCXO: – Pierce Oscillator – Two frequency control capacitors



Three frequency control mechanisms: – Bang-bang control: • switched capacitor

– Integral control: • voltage controlled n-well capacitor

– Frequency centering: • four binary weighted switched capacitors. (Not under the PLL loop control)

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PLL Applications

15

VXCO Tuning •

Ideally the crystal should be loaded by a “short circuit”: –

The oscillation frequency can be controlled by changing the loading capacitance:



The amount of control is very reduced:

The oscillation frequency will be the resonance frequency of the crystal: fm.





In practice the oscillator presents a loading capacitance Ccircuit to the crystal: –

– Cm : 5.9 fF;

The oscillation frequency is then higher than fm;



– Cm is orders of magnitude smaller than Ccircuit;

Crystal manufacturing takes into account the loading capacitance;

– Ccircuit : 3.4 pF to 5.5 pF. •

Good: intrinsically low bandwidth PLL;



Bad: small locking range;

fO = fm 1 +

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PLL Applications

Cm C circuit

16

VCXO Frequency Centering •





Lock acquisition, two phases: –

Frequency centering;



Standard frequency pull-in and phase lock cycle.

Frequency centering: –

After start-up, reset or unlocked operation detected;



Frequency-only detector used.

Frequency centering operations: 1. The bang-bang loop is disabled; 2. The VCXO control voltage forced to its mid range value; 3. A binary search is made to decide on the value of the frequency centering capacitor; 4. Once the value found, control is passed to the PLL control loop.

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PLL Applications

17

Comparing Almost Identical Frequencies Which frequency is higher? •





Two counters: –

One driven by the reference frequency: f0;



The other driven by the VCO frequency: f0 + ∆f.

Which one reaches “N” first? –

Reference first: VCO slow;



VCO first: VCO fast.

For the smallest frequency difference ∆f to be resolved make sure that one of the counters will finish Xck clock cycles before the other: –

Start phase;



Metastability;



Asynchronous reset;



Etc.

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PLL Applications

18

Frequency Resolution •

N clock cycles are required to resolve a frequency difference ∆F between the reference and the VCO signals:

N= • •

The counter size is: QPLL example:

X CK  f0  − 1  f + ∆f    0

Number of bits = log 2 ( N )

– f0 = 40.972483 MHz; – Digital control LSB: ∆f = 0.2 kHz; – N = 819 456 (clock cycles); – Counter ≈ 20 bits; – The PLL has 4 digital calibration bits; – A binary search is implemented in the Frequency Calibration Algorithm ⇒ 4 frequency decision cycles; – Two dummy frequency decision cycles were introduced to allow frequency stabilization after power-up (maybe strictly not necessary); – Total 6 frequency decision cycles are executed during frequency calibration; – Frequency calibration takes (approximately): 6 × 819 456 × 25 ns = 157 ms

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PLL Applications

19

Jitter

Reference: Idle

Reference: Data + Triggers

σ= 63 ps

σ= 89 ps

PP = 546 ps

PP = 584 ps

Jitter components above 7 kHz are filtered.

PLL Output: Idle

Below 7 kHz the PLL tracks the input phase fluctuations

PLL Output: Data + Triggers

σ= 20 ps

σ= 22 ps

PP = 159 ps

PP = 206 ps

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PLL Applications

20

References Two PLL ‘classics’: 

F. M. Gardner, “Phaselock Techniques,” John Wiley & Sons 1979, ISBN 0-471-04294-3



F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858, November 1980

Bang-bang PLLs: 

R. C. Walker et al., “A Two-Chip 1.5-Gbd Serial Link Interface”, IEEE Journal on Solid-State Circuits, vol. 27, no. 12, pp. 1805-1810, December 1992



J. Lee, K. S. Kundert and B. Razavi, “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, September 2004, pp. 1571-1580



R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” to be published (see: http://www.omnisterra.com/walker/index.html)

Self biasing techniques (DLL & PLL): 

John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biasing Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, November 1996

PLL books: 

R. E. Best, “Phase-Locked Loops Theory, Design, and Applications,” McGraw-Hill Book Company 1984, ISBN 0-07-005050-3



D. H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice Hall 1991, ISBN 0-13-662743-9



B. Razavi, “Monolithic Phase-Locked Loops and Clock Recovery Circuits Theory and Design,” IEEE Press 1996, ISBN 0-7803-1149-3

Books, not specifically on PLLs but that contain a good introduction: 

D. A. Johns and K. Martin, “Analog Integrated Circuit Design,” John Wiley & Sons 1997, ISBN 0471-14448-7 – Chapter 16

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PLL Applications

21

References Phase detectors: 

J. D. H. Alexander, “Clock Recovery from Random Binary Signals,” Electronics Letters, vol. 11, no. 22, pp. 541-542, October 1975



C. R. Hogge, ‘A Self-Correcting Clock Recovery Circuit,’ J. Lightwave technology, vol. LT-3, no. 6, pp.1312-1314, 1985

VCO phase noise: 

B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal on Solid-State Circuits, vol. 31, no. 3, pp. 331-343, March 1996



J. A. McNeil, “Jitter in Ring Oscillators,” IEEE Journal on Solid-State Circuits, vol. 32, no. 2 , June 1997, pp. 807-879



T. H. Lee and A. Hajimiri, “Phase Noise in Oscillators, A Tutorial” Invited Paper, IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp. 326-336, March 2000

Time-to-digital converters: 

M. Mota, “Design and Characterization of CMOS High-Resolution Time-to-Digital Converters,” Ph.D. thesis, October 2000, Lisbon, Portugal. (PDF file can be found at: http://paulo.moreira.free.fr/microelectronics/padova/padova.htm)

Edited collection of papers: 

“Monolithic Phase-Locked Loops and Clock Recovery Circuits Theory and Design,” Edited by Behzad Razavi, IEEE Press, 1996, ISBN 0-7803-1149-3



“Phase-Locking in High-Performance Systems From Devices to Architectures,” Edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7

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PLL Applications

22

On the Web 

This presentation: –



http://paulo.moreira.free.fr/microelectronics/padova/padova.htm

Many sites dealing with PLLs can be found on the web. Here are some of the my favorites: –

http://www.omnisterra.com/walker/index.html



http://www.circuitsage.com/pll.html



http://www.designers-guide.org/



http://www.ife.ee.ethz.ch/~ichsc/ichsc_chapter11.pdf



http://www.analog.com/library/analogDialogue/archives/33-03/phase/



http://www.web-ee.com/primers/files/pll_tut_talk.pdf

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PLL Applications

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