Power Design Guide S3C6410X RISC Microprocessor October 7, 2009 Preliminary REV 0.91
Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2007 Samsung Electronics, Inc. All Rights Reserved
6410X_POWER DESIGN GUIDE PRELIMINARY REV 0.91
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.
"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product
. S3C6410X RISC Microprocessor Power Design Guide, Preliminary Revision 0.9a Copyright © 2007-2009 Samsung Electronics Co.,Ltd. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City Gyeonggi-Do, Korea 446-711
Home Page: http://www.samsungsemi.com/ E-Mail:
[email protected] Printed in the Republic of Korea
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Revision History Revision No
Description of Change
Refer to
Author(s)
Date
0.00
- Initial Release for review
-
S.K. Kim
2008-05-13
0.03
- DC Spec. is changed - Notification is added
-
S.K.Kim
2008-07-25
0.04
- Power Sequence is updated
-
S.K.Kim
2008-08-20
0.05
- DVFS Guideline at sync. Mode is added
-
S.K.Kim
2008-09-23
0.06
- Power Consumption is added
-
S.K.Kim
2008-09-27
0.7
- Redundant information is removed
-
S.K.Kim
2009-05-14
0.7a
- DVFS Minimum Voltage is added
-
S.K.Kim
2009-07-22
0.8
- Power on Sequence is modified
-
S.K.Kim
2009-08-06
0.91
- Power on Sequence is modified - Operating Voltage is modified
-
S.K.Kim
2009-10-07
NOTE: Revised parts are written in blue.
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Table of Contents 1. PRODUCT OVERVIEW ............................................................................................................................ 5 2. RECOMMENDED OPERATING CONDITIONS ....................................................................................... 6 3. RECOMMEND SYSTEM POWER DESIGN ............................................................................................. 7 4. CIRCUIT GUIDE FOR DVS SCHEME...................................................................................................... 8 5. TIMING CHARTS WITH DVFS ................................................................................................................. 9 5.1. Typical DVFS Level Definition ........................................................................................................ 9 5.1.1. Typical DVFS Transition Table @ 533Mhz Synchronous and Asynchronous Mode......... 9 5.1.2. Typical DVFS Transition Table @ 800Mhz Synchronous and Asynchronous Mode......... 9 5.2. Typical DVFS Transition Diagram .................................................................................................. 10 5.2.1. Typical DVFS Transition Diagram @ 533, 800Mhz ................................................................ 10 6. POWER ON AND OFF SEQUENCE ........................................................................................................ 15 7. PLL DESIGN GUIDE ................................................................................................................................ 19 7.1. APLL/MPLL Specification ............................................................................................................... 19 7.2. EPLL Specification .......................................................................................................................... 20 7.3. USB OTG 2.0 PLL Specification ..................................................................................................... 21 7.4. TV OUT Clock Specification............................................................................................................ 21 APPENDIX .................................................................................................................................................... 22 A. Example of Changing Divider Code ................................................................................................. 22 B. Power Requirement............................................................................................................................ 23
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1. PRODUCT OVERVIEW This document describes S3C6410 power design guide for circuit designer. It shows as follows, -
recommend DC operating conditions
-
recommend system power design
-
power on/off sequence
-
pll design guide
-
power consumption data
It will help you design your system properly.
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2. RECOMMENDED OPERATING CONDITIONS Table 1-1. Recommended Operating Conditions Parameter DC Supply Voltage for Alive Block
DC Supply Voltage for Core Block
Symbol
Min
Typ
Max
VDDALIVE VDDAPLL VDDMPLL VDDEPLL
1.15
1.2
1.25
1.15
1.2
1.25
0.95
1.05
1.3
1.15
1.25
1.3
66MHz
0.95
1.05
-
133MHz
0.95
1.05
-
1.0
1.10
-
1.05
1.15
-
533MHz
1.05
1.15
-
800MHz
1.25
1.35
Note 2)
66MHz
VDDINT
133MHz
Note 1)
266MHz
VDDARM Note 1)
400MHz
V
DC Supply Voltage for Memory Interface0 (NOR/NAND/OneNAND/CF)
VDDMEM0
1.7
1.8~3.3
3.6
DC Supply Voltage for Memory Interface1 (DRAM)
VDDMEM1
1.75
1.8/2.5
2.7
VDDMMC/VDDHI/VD DLCD/VDDPCM/VDD EXT/VDDSYS
1.7
1.8/2.5/3.3
3.6
DC Supply Voltage for RTC
VDDRTC
1.7
1.8/2.5/3.0
3.3
DC Supply Voltage for ADC
VDDADC
3.0
3.3
3.6
DC Supply Voltage for DAC
VDDDAC
3.0
3.3
3.6
DC Supply Voltage for USB OTG Phy 3.3V
VDDOTG
3.3 - 5%
3.3
3.3 + 5%
DC Supply Voltage for USB OTG Internal
VDDOTGI
1.2 - 5%
1.2
1.2 + 5%
VDDUH
3.0
3.3
3.6
TA
Extended
DC Supply Voltage for I/O Block
DC Supply Voltage for USB Host Operating Temperature
Unit
-25 to 85
o
C
Note 1) Even though each value is higher than that is described in user’s manual, We strongly recommend that proposed typical voltage should be adopted because of PMIC’s ripple characteristics. Note 2) VDDARM shouldn’t be supplied over 1.35V continuously. There are no abnormal operation on 6410 when VDDARM is supplied up to 1.4V instantaneously.
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3. RECOMMEND SYSTEM POWER DESIGN V.V-DC-DC Battery 3.8V/ xx mAh
V.V-DC-DC FET
S3C6410X VDDARM
VDDINT
VDDINT
VDDxPLL
VDDAPLL/VDDMPLL/V DDEPLL VDDALIVE
VDDALIVE
LDO
VDDRTC
LDO DC/DC
VDDMEMx VDDADC/DAC/UH
LDO
IO Voltage
LDO LDO
VDDARM
VDDOTG EN
GPIO Control
LDO
VDDOTGI EN
VDDRTC VDDMEM0 VDDMEM1 VDDADC/VDDDAC/V DDUH VDDMMC/VDDHI/VDD LCD/VDDPCM/VDDEX T/VDDSYS VDDOTG VDDOTGI
GPIO Control
Figure 1. Power Scheme Diagram VDDALIVE is fed into FET(MosFET Switch) to generate VDDxPLL. FET switch should be turned on when VDDINT is supplied. FET switch should be turned off when CPU is in sleep mode.
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4. CIRCUIT GUIDE FOR DVS SCHEME The diagram described in figure 2 is a example to implement h/w configuration for DVFS. VDDARM and VDDINT can be supplied directly from PMIC if the voltage of them can be variable with software setting.
VDD33V
VDDARM
VDDARM
R1 DC/ DC Converter
R2
R2 : DVS OFF Resistor Value R3 : DVS ON Resistor Value
R3
VDDARM is depended by ARM Frequency
nGPIO1 On: / w DVS Off: / wo DVS
FB
VDD33V
VDDINT
VDDINT
R1 DC/ DC Converter
R2
R2 : R3 :
Resistor Value(133MHz) Resistor Value(66MHz)
R3 nGPIO2 On: / w DVS Off: / wo DVS
FB
Figure 2. An example of generating variable voltage
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5. TIMING CHARTS WITH DVFS 5.1. Typical DVFS Level Definition 5.1.1. Typical DVFS Transition Table @ 533Mhz Synchronous and Asynchronous Mode LEVEL L0(Fast)
FoutAPLL
FoutMPLL
ARMCLK(MHz) 532
HCLK(MHz) 133
PCLK(MHz) 66
266
133
66
266
133
66
L3
133
133
66
AL1
133
66
66
AL2
66
66
66
L1 L2
532
266
Remark
Note)
Note) If AL1 or AL2 is used, refresh cycle should be set based on 66MHz at initial setting
5.1.2. Typical DVFS Transition Table @ 800Mhz Synchronous and Asynchronous Mode LEVEL L0(Fast)
FoutAPLL
FoutMPLL
ARMCLK(MHz) 800
HCLK(MHz) 133
PCLK(MHz) 66
400
133
66
266
133
66
L3
133
133
66
AL1
133
66
66
AL2
66
66
66
L1 L2
800
266
Remark
Note)
Note) If AL1 or AL2 is used, refresh cycle should be set based on 66MHz at initial setting
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5.2. Typical DVFS Transition Diagram 5.2.1. Typical DVFS Transition Diagram @ 533, 800Mhz
L3
L0
L2
L1
Figure 3. A transition diagram when cpu is in 533, 800Mhz DVFS level can be switched by changing clock divider. External access by ARM is not permitted when clock divider is changed at synchronous mode. It is implemented easily using IMB(Instruction Memory Barrier) and DMB(Data Memory Barrier). Refer to attached assembly code, ChangeDivider()
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5.3. Timing diagram with DVFS
xtal:xtal:xtal Slow
533:133:33
0:133:33
533:133:33
Normal
Idle
Normal
0V
(1) Power is turned on and program is started under slow clock (2) After locktime(caused by PMS setting), the system runs at high speed(533MHz) (3) Enter Idle mode (4) Wake-up from Idle mode
Figure 5. Transition between Normal and Idle mode when 533:133MHz Case
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Figure 6. DVFS example by changing clock divider when 533:133MHz Case
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Figure 7. DVFS with Idle state example by changing clock divider when 533:133MHz Case
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Figure 9. DVFS example by changing PMS value during
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6. POWER ON AND OFF SEQUENCE
tOA
VDD_IO Unknown State
User-Defined State
Reset State
IO State tAE
tAI
VDDALIVE Unknown State
XPWRRGTON VDDARM/ VDDINT
tOSC
OSC(XTIpll) tOR
XnRESET
S/W defines GPIO
Figure 10-a. Power on sequence in case of normal discrete power solution (Non-PMIC)
Symbol
Description
Min
Typical
Max
Units
tOA
VDD_IO to VDDALIVE
0
Ms
tAI
XPWRRGTON to VDDARM/VDDINT
It depend on Regulator
Ms
tAE
VDDALIVE to XPWRRGTON
0
Ns
tOSC
VDDINT/VDDARM/VDDPLL to Oscillator stabilization
tOR
Oscillator stabilization to XnRESET high
10 Note)
10
Ms Cycle
Note) VDD_IO=VDDMMC & VDDHI & VDDLCD & VDDPCM & VDDEXT & VDDSYS & VDDATA & VDDUH & VDDM0 & VDDM1 VDDPLL=VDDMPLL & VDDEPLL & VDDAPLL tOSC is depend on characteristics of crystal, pcb and capacitance.
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tAC
VDDALIVE User-Defined State
Reset State
IO State
VDDARM/ VDDINT
tCI
tOSC
VDD_IO OSC(XTIpll)
tOR
XnRESET
S/W defines GPIO
Figure 10-b. Power on sequence in case of PMIC solution
Symbol
Description
Min
Typical
Max
Units
tAC
VDDALIVE to VDD_ARM/INT
0
Ms
tCI
VDD_ARM/INT to VDD_IO
0
Us
tOSC
VDDINT/VDDARM/VDDPLL to Oscillator stabilization
tOR
Oscillator stabilization to XnRESET high
Note) 10
Ms Cycle
Note) VDD_IO=VDDMMC & VDDHI & VDDLCD & VDDPCM & VDDEXT & VDDSYS & VDDATA & VDDUH & VDDM0 & VDDM1 VDDPLL=VDDMPLL & VDDEPLL & VDDAPLL tOSC is depend on characteristics of crystal, pcb and capacitance.
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Figure 11. Power off sequence
Symbol Description Min TYP Max Units tloa VDD_IO to VDDALIVE 0 ms tloi VDD_IO to VDDINT/VDDARM/VDDPLL 0 ms Note) VDD_IO=VDDMMC & VDDHI & VDDLCD & VDDPCM & VDDEXT & VDDSYS & VDDATA & VDDUH & VDDM0 & VDDM1 VDDPLL=VDDMPLL & VDDEPLL & VDDAPLL
I/O signal has unknown state which is described in the Figure 10-a. I/O signal may occur glitch at power on stage. For example, when using this I/O as LED on/off control signal, it causes unwanted flickering. To protect this glitch, System designer can use external AND gate device with nRESET signal.
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Normal Mode
Sleep Mode
Reset
Normal Mode
VDD_Opx, cam, lcd, sd, sdram, sram, adc, rtc VDDA33T, A33C, UDEV
Turn on USB power when use USB
VDDarm /int/pll PWR_EN nRESET PWRSETCNT RSTOUT EXTCLK or XTIpll Pll lock time VCO Output
SYSCLK Sleep mode is initiated
Wakeup Event
Figure 12 Sleep mode & wakeup sequence Note) VDD_IO : VDDMMC, VDDHI, VDDLCD, VDDPCM, VDDEXT, VDDSYS, VDDMEMx, VDDSS PWR_EN : Signal at XPWRRGTON pin
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7. PLL DESIGN GUIDE XXTI
XrtxXTI
XXTO
XrtcXTO 5M-ohm
1M-ohm
X27MXTI
XotgTI
X27MXTO
XotgTO 1M-ohm
1M-ohm Figure 13 Crystal Design Guide
7.1. APLL/MPLL Specification The output frequencies of APLL/MPLL can be calculated using the following equations: FOUT = MDIV X FIN / (PDIV X 2SDIV) MDIV: 64 ≤ MDIV ≤ 1023 PDIV: 1 ≤ PDIV ≤ 63 SDIV: 0 ≤ SDIV ≤ 5 FVCO =(MDIV X FIN / PDIV): 800MHz ≤ FVCO ≤ 1600MHz FIN : 10MHz ≤ FIN ≤ 20MHz NOTE ) Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL value recommendation table. If you have to use other values, please contact us.
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FIN (MHz)
Target FOUT (MHz)
MDIV
PDIV
SDIV
12
266
266
3
2
12
400
400
3
2
12
533
266
3
1
400
3
1
12 800 Usual Conditions for MPLL & Clock Generator
PLL & Clock Generator generally uses the following conditions. Loop filter capacitance
CLF
Need not Loop Filter Capacitance
-
10 – 20 MHz
CEXT
15 – 22 pF
External X-tal frequency External capacitance used for X-tal
7.2. EPLL Specification The output frequencies of EPLL can be calculated using the following equations: FOUT = (MDIV + KDIV / 216) X FIN / (PDIV X 2SDIV) where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions : MDIV: 16 ≤ MDIV ≤ 255 PDIV: 1 ≤ PDIV ≤ 63 KDIV: 0 ≤ KDIV ≤ 65535 SDIV: 0 ≤ SDIV ≤ 4 FVCO (= (MDIV + KDIV / 216) X FIN / PDIV) : 300MHz ≤ FVCO ≤ 600MHz FOUT : 20MHz ≤ FOUT ≤ 600MHz FIN : 10MHz ≤ FIN ≤ 20MHz NOTE ) Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL value recommendation table. If you have to use other values, please contact us. FIN (MHz)
FOUT (MHz)
MDIV
PDIV
SDIV
KDIV
12
36
48
1
4
0
12
48
32
1
3
0
12
60
40
1
3
0
12
72
48
1
3
0
12
84
28
1
2
0
12
96
32
1
2
0
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Usual Conditions for EPLL & Clock Generator PLL & Clock Generator generally uses the following conditions. Loop filter capacitance External X-tal frequency External capacitance used for X-tal
CLF
XpllEFILTER: 1.8nF
-
10 – 20 MHz
CEXT
15 – 22 pF
7.3. USB OTG 2.0 PLL Specification PLL & Clock Generator generally uses the following conditions. REXT
R
44.2Ω ± 1%
VDDOTG
V
3.3 ± 5%
VDDOTGI
V
1.2 ± 5%
External X-tal frequency
-
12M/24M/48 MHz recommend a quartz crystal
External capacitance used for X-tal
CEXT
12M/24M - 20 pF 48M - 16 pF
Note ) (1) For usb2.0 device, user should be obey a layout rule of pcb.
7.4. TV OUT Clock Specification PLL & Clock Generator generally uses the following conditions. XdacIREF
R
6.49 KΩ ± 1%
VDDDAC
V
3.3 ± 0.3V
External X-tal frequency
-
27MHz 15pF
External capacitance used for X-tal
CEXT
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APPENDIX A. Example of Changing Divider Code ;--------------------------------- -----------------------------------------------------------------; Enable Branch Prediction ;--------------------------------- -----------------------------------------------------------------LEAF_ENTRY System_EnableBP mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_BP mcr p15,0,r0,c1,c0,0 mov pc, lr ENTRY_END ;--------------------------------- -----------------------------------------------------------------; ChangeDivider ;--------------------------------- -----------------------------------------------------------------EXPORT ChangeDivider ; r0=the value of clock divider ChangeDivider PROC stmfd sp!, {r0-r5} ldr r1,=0x7e00f020 mov r2, #0 mov r3, #0 loopcd mov r4, #0 mcr p15, 0, r2, c7, c10, 4 ; data synchronization barrier instruction mcr p15, 0, r2, c7, c10, 5 ; data memory barrier operation cmp r3, #1 streq r0, [r1] mcr p15, 0, r2, c7, c5, 4 ; flush prefetch buffer loop1000 add r4, r4, #1 cmp r4, #0x1000 bne loop1000 cmp r3, #1 add r3, r3, #1 bne loopcd ldmfd sp!, {r0-r5} mov pc,lr ENDP ;--------------------------------- -----------------------------------------------------------------; Disable Branch Prediction ;--------------------------------- -----------------------------------------------------------------LEAF_ENTRY System_DisableBP mrc p15,0,r0,c1,c0,0 bic r0,r0,#R1_BP mcr p15,0,r0,c1,c0,0 mov pc, lr ENTRY_END Usage) System_EnableBP(); ChangeDivider(); System_DisableBP();
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B. Power Requirement
Power Name
Voltage [V]
Max. Current [mA]
VDDALIVE
1.2
2
VDDAPLL/VDDMPLL/VDDEPLL
1.2
10
VDDARM
1.2
900
VDDINT
1.3
500
VDDMEM0
3.3
50
VDDMEM1
1.8
100
VDDMMC/VDDHI/VDDLCD/VDDPCM/VDDEXT/VDDSYS
3.3
150
VDDRTC
1.8
1
VDDADC
3.3
10
VDDDAC
3.3
20
VDDOTG
3.3
20
VDDOTGI
1.2
20
VDDUH
3.3
30
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